2 * Copyright (C) 2008 Renesas Solutions Corp.
3 * Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
4 * Copyright (C) 2007 Kenati Technologies, Inc.
6 * board/sh7763rdp/lowlevel_init.S
8 * SPDX-License-Identifier: GPL-2.0+
14 #include <asm/processor.h>
15 #include <asm/macro.h>
24 write32 WDTCSR_A, WDTCSR_D /* Watchdog Control / Status Register */
26 write32 WDTST_A, WDTST_D /* Watchdog Stop Time Register */
28 write32 WDTBST_A, WDTBST_D /*
30 * Watchdog Base Stop Time Register
33 write32 CCR_A, CCR_CACHE_ICI_D /* Address of Cache Control Register */
34 /* Instruction Cache Invalidate */
36 write32 MMUCR_A, MMU_CONTROL_TI_D /* MMU Control Register */
37 /* TI == TLB Invalidate bit */
39 write32 MSTPCR0_A, MSTPCR0_D /* Address of Power Control Register 0 */
41 write32 MSTPCR1_A, MSTPCR1_D /* Address of Power Control Register 1 */
43 write32 RAMCR_A, RAMCR_D
50 mov.l @r1, r2 /* execute two reads after setting MMSELR */
54 /* issue memory read */
55 mov.l DDRSD_START_A, r1 /* memory address to read*/
59 write32 MIM8_A, MIM8_D
61 write32 MIMC_A, MIMC_D1
63 write32 STRC_A, STRC_D
65 write32 SDR4_A, SDR4_D
67 write32 MIMC_A, MIMC_D2
73 write32 SCR4_A, SCR4_D3
75 write32 SCR4_A, SCR4_D2
77 write32 SDMR02000_A, SDMR02000_D
79 write32 SDMR00B08_A, SDMR00B08_D
81 write32 SCR4_A, SCR4_D2
83 write32 SCR4_A, SCR4_D4
90 write32 SCR4_A, SCR4_D4
97 write32 SDMR00308_A, SDMR00308_D
99 write32 MIMC_A, MIMC_D3
111 write32 CCR_A, CCR_CACHE_D_2 /* Address of Cache Control Register */
116 write32 CS0BCR_A, CS0BCR_D
118 write32 CS1BCR_A, CS1BCR_D
120 write32 CS2BCR_A, CS2BCR_D
122 write32 CS4BCR_A, CS4BCR_D
124 write32 CS5BCR_A, CS5BCR_D
126 write32 CS6BCR_A, CS6BCR_D
128 write32 CS0WCR_A, CS0WCR_D
130 write32 CS1WCR_A, CS1WCR_D
132 write32 CS2WCR_A, CS2WCR_D
134 write32 CS4WCR_A, CS4WCR_D
136 write32 CS5WCR_A, CS5WCR_D
138 write32 CS6WCR_A, CS6WCR_D
140 write32 CS5PCR_A, CS5PCR_D
142 write32 CS6PCR_A, CS6PCR_D
151 write16 PSEL0_A, PSEL0_D
153 write16 PSEL1_A, PSEL1_D
155 write32 ICR0_A, ICR0_D
157 stc sr, r0 /* BL bit off(init=ON) */
168 DELAY200_D: .long 17800
170 CCR_A: .long 0xFF00001C
171 MMUCR_A: .long 0xFF000010
172 RAMCR_A: .long 0xFF000074
174 /* Low power mode control */
175 MSTPCR0_A: .long 0xFFC80030
176 MSTPCR1_A: .long 0xFFC80038
179 WDTST_A: .long 0xFFCC0000
180 WDTCSR_A: .long 0xFFCC0004
181 WDTBST_A: .long 0xFFCC0008
184 MMSELR_A: .long 0xFE600020
185 BCR_A: .long 0xFF801000
186 CS0BCR_A: .long 0xFF802000
187 CS1BCR_A: .long 0xFF802010
188 CS2BCR_A: .long 0xFF802020
189 CS4BCR_A: .long 0xFF802040
190 CS5BCR_A: .long 0xFF802050
191 CS6BCR_A: .long 0xFF802060
192 CS0WCR_A: .long 0xFF802008
193 CS1WCR_A: .long 0xFF802018
194 CS2WCR_A: .long 0xFF802028
195 CS4WCR_A: .long 0xFF802048
196 CS5WCR_A: .long 0xFF802058
197 CS6WCR_A: .long 0xFF802068
198 CS5PCR_A: .long 0xFF802070
199 CS6PCR_A: .long 0xFF802080
200 DDRSD_START_A: .long 0xAC000000
203 ICR0_A: .long 0xFFD00000
206 MIM8_A: .long 0xFE800008
207 MIMC_A: .long 0xFE80000C
208 SCR4_A: .long 0xFE800014
209 STRC_A: .long 0xFE80001C
210 SDR4_A: .long 0xFE800034
211 SDMR00308_A: .long 0xFE900308
212 SDMR00B08_A: .long 0xFE900B08
213 SDMR02000_A: .long 0xFE902000
216 PSEL0_A: .long 0xFFEF0070
217 PSEL1_A: .long 0xFFEF0072
219 CCR_CACHE_ICI_D:.long 0x00000800
220 CCR_CACHE_D_2: .long 0x00000103
221 MMU_CONTROL_TI_D:.long 0x00000004
222 RAMCR_D: .long 0x00000200
223 MSTPCR0_D: .long 0x00000000
224 MSTPCR1_D: .long 0x00000000
226 MMSELR_D: .long 0xa5a50000
227 BCR_D: .long 0x00000000
228 CS0BCR_D: .long 0x77777770
229 CS1BCR_D: .long 0x77777670
230 CS2BCR_D: .long 0x77777670
231 CS4BCR_D: .long 0x77777670
232 CS5BCR_D: .long 0x77777670
233 CS6BCR_D: .long 0x77777670
234 CS0WCR_D: .long 0x7777770F
235 CS1WCR_D: .long 0x22000002
236 CS2WCR_D: .long 0x7777770F
237 CS4WCR_D: .long 0x7777770F
238 CS5WCR_D: .long 0x7777770F
239 CS6WCR_D: .long 0x7777770F
240 CS5PCR_D: .long 0x77000000
241 CS6PCR_D: .long 0x77000000
242 ICR0_D: .long 0x00E00000
243 MIM8_D: .long 0x00000000
244 MIMC_D1: .long 0x01d10008
245 MIMC_D2: .long 0x01d10009
246 MIMC_D3: .long 0x01d10209
247 SCR4_D1: .long 0x00000001
248 SCR4_D2: .long 0x00000002
249 SCR4_D3: .long 0x00000003
250 SCR4_D4: .long 0x00000004
251 STRC_D: .long 0x000f3980
252 SDR4_D: .long 0x00000300
253 SDMR00308_D: .long 0x00000000
254 SDMR00B08_D: .long 0x00000000
255 SDMR02000_D: .long 0x00000000
256 PSEL0_D: .word 0x00000001
257 PSEL1_D: .word 0x00000244
258 SR_MASK_D: .long 0xEFFFFF0F
259 WDTST_D: .long 0x5A000FFF
260 WDTCSR_D: .long 0xA5000000
261 WDTBST_D: .long 0x55000000