1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2011 Renesas Solutions Corp.
12 #include <asm/processor.h>
16 #include <spi_flash.h>
20 puts("BOARD: R0P7757LC0030RL board\n");
25 static void init_gctrl(void)
27 struct gctrl_regs *gctrl = GCTRL_BASE;
28 unsigned long graofst;
30 graofst = (SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_GRA_OFFSET) >> 24;
31 writel(graofst | 0x20000f00, &gctrl->gracr3);
34 static int init_pcie_bridge_from_spi(void *buf, size_t size)
36 #ifdef CONFIG_DEPRECATED
37 struct spi_flash *spi;
39 unsigned long pcie_addr;
41 spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);
43 printf("%s: spi_flash probe error.\n", __func__);
48 pcie_addr = SH7757LCR_PCIEBRG_ADDR_B0;
50 pcie_addr = SH7757LCR_PCIEBRG_ADDR;
52 ret = spi_flash_read(spi, pcie_addr, size, buf);
54 printf("%s: spi_flash read error.\n", __func__);
62 printf("No SPI support so no PCIe support\n");
67 static void init_pcie_bridge(void)
69 struct pciebrg_regs *pciebrg = PCIEBRG_BASE;
70 struct pcie_setup_regs *pcie_setup = PCIE_SETUP_BASE;
74 unsigned long pcie_size;
76 if (!(readw(&pciebrg->ctrl_h8s) & 0x0001))
80 pcie_size = SH7757LCR_PCIEBRG_SIZE_B0;
82 pcie_size = SH7757LCR_PCIEBRG_SIZE;
84 data = malloc(pcie_size);
86 printf("%s: malloc error.\n", __func__);
89 if (init_pcie_bridge_from_spi(data, pcie_size)) {
94 if (data[0] == 0xff && data[1] == 0xff && data[2] == 0xff &&
97 printf("%s: skipped initialization\n", __func__);
101 writew(0xa501, &pciebrg->ctrl_h8s); /* reset */
102 writew(0x0000, &pciebrg->cp_ctrl);
103 writew(0x0000, &pciebrg->cp_addr);
105 for (i = 0; i < pcie_size; i += 2) {
106 tmp = (data[i] << 8) | data[i + 1];
107 writew(tmp, &pciebrg->cp_data);
110 writew(0xa500, &pciebrg->ctrl_h8s); /* start */
112 writel(0x00000001, &pcie_setup->pbictl3);
117 static void init_usb_phy(void)
119 struct usb_common_regs *common0 = USB0_COMMON_BASE;
120 struct usb_common_regs *common1 = USB1_COMMON_BASE;
121 struct usb0_phy_regs *phy = USB0_PHY_BASE;
122 struct usb1_port_regs *port = USB1_PORT_BASE;
123 struct usb1_alignment_regs *align = USB1_ALIGNMENT_BASE;
125 writew(0x0100, &phy->reset); /* set reset */
126 /* port0 = USB0, port1 = USB1 */
127 writew(0x0002, &phy->portsel);
128 writel(0x0001, &port->port1sel); /* port1 = Host */
129 writew(0x0111, &phy->reset); /* clear reset */
131 writew(0x4000, &common0->suspmode);
132 writew(0x4000, &common1->suspmode);
134 #if defined(__LITTLE_ENDIAN)
135 writel(0x00000000, &align->ehcidatac);
136 writel(0x00000000, &align->ohcidatac);
140 static void set_mac_to_sh_eth_register(int channel, char *mac_string)
142 struct ether_mac_regs *ether;
143 unsigned char mac[6];
146 string_to_enetaddr(mac_string, mac);
149 ether = ETHER0_MAC_BASE;
151 ether = ETHER1_MAC_BASE;
153 val = (mac[0] << 24) | (mac[1] << 16) | (mac[2] << 8) | mac[3];
154 writel(val, ðer->mahr);
155 val = (mac[4] << 8) | mac[5];
156 writel(val, ðer->malr);
159 static void set_mac_to_sh_giga_eth_register(int channel, char *mac_string)
161 struct ether_mac_regs *ether;
162 unsigned char mac[6];
165 string_to_enetaddr(mac_string, mac);
168 ether = GETHER0_MAC_BASE;
170 ether = GETHER1_MAC_BASE;
172 val = (mac[0] << 24) | (mac[1] << 16) | (mac[2] << 8) | mac[3];
173 writel(val, ðer->mahr);
174 val = (mac[4] << 8) | mac[5];
175 writel(val, ðer->malr);
178 /*****************************************************************
179 * This PMB must be set on this timing. The lowlevel_init is run on
180 * Area 0(phys 0x00000000), so we have to map it.
182 * The new PMB table is following:
183 * ent virt phys v sz c wt
184 * 0 0xa0000000 0x40000000 1 128M 0 1
185 * 1 0xa8000000 0x48000000 1 128M 0 1
186 * 2 0xb0000000 0x50000000 1 128M 0 1
187 * 3 0xb8000000 0x58000000 1 128M 0 1
188 * 4 0x80000000 0x40000000 1 128M 1 1
189 * 5 0x88000000 0x48000000 1 128M 1 1
190 * 6 0x90000000 0x50000000 1 128M 1 1
191 * 7 0x98000000 0x58000000 1 128M 1 1
193 static void set_pmb_on_board_init(void)
195 struct mmu_regs *mmu = MMU_BASE;
198 writel(0x00000004, &mmu->mmucr);
200 /* delete PMB for SPIBOOT */
201 writel(0, PMB_ADDR_BASE(0));
202 writel(0, PMB_DATA_BASE(0));
204 /* add PMB for SDRAM(0x40000000 - 0x47ffffff) */
205 /* ppn ub v s1 s0 c wt */
206 writel(mk_pmb_addr_val(0xa0), PMB_ADDR_BASE(0));
207 writel(mk_pmb_data_val(0x40, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(0));
208 writel(mk_pmb_addr_val(0xb0), PMB_ADDR_BASE(2));
209 writel(mk_pmb_data_val(0x50, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(2));
210 writel(mk_pmb_addr_val(0xb8), PMB_ADDR_BASE(3));
211 writel(mk_pmb_data_val(0x58, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(3));
212 writel(mk_pmb_addr_val(0x80), PMB_ADDR_BASE(4));
213 writel(mk_pmb_data_val(0x40, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(4));
214 writel(mk_pmb_addr_val(0x90), PMB_ADDR_BASE(6));
215 writel(mk_pmb_data_val(0x50, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(6));
216 writel(mk_pmb_addr_val(0x98), PMB_ADDR_BASE(7));
217 writel(mk_pmb_data_val(0x58, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(7));
222 struct gether_control_regs *gether = GETHER_CONTROL_BASE;
224 set_pmb_on_board_init();
226 /* enable RMII's MDIO (disable GRMII's MDIO) */
227 writel(0x00030000, &gether->gbecont);
235 int board_mmc_init(bd_t *bis)
237 return mmcif_mmc_init();
240 static int get_sh_eth_mac_raw(unsigned char *buf, int size)
242 #ifdef CONFIG_DEPRECATED
243 struct spi_flash *spi;
246 spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);
248 printf("%s: spi_flash probe error.\n", __func__);
252 ret = spi_flash_read(spi, SH7757LCR_ETHERNET_MAC_BASE, size, buf);
254 printf("%s: spi_flash read error.\n", __func__);
264 static int get_sh_eth_mac(int channel, char *mac_string, unsigned char *buf)
266 memcpy(mac_string, &buf[channel * (SH7757LCR_ETHERNET_MAC_SIZE + 1)],
267 SH7757LCR_ETHERNET_MAC_SIZE);
268 mac_string[SH7757LCR_ETHERNET_MAC_SIZE] = 0x00; /* terminate */
273 static void init_ethernet_mac(void)
282 printf("%s: malloc error.\n", __func__);
285 get_sh_eth_mac_raw(buf, 256);
288 for (i = 0; i < SH7757LCR_ETHERNET_NUM_CH; i++) {
289 get_sh_eth_mac(i, mac_string, buf);
291 env_set("ethaddr", mac_string);
293 sprintf(env_string, "eth%daddr", i);
294 env_set(env_string, mac_string);
297 set_mac_to_sh_eth_register(i, mac_string);
300 /* Gigabit Ethernet */
301 for (i = 0; i < SH7757LCR_GIGA_ETHERNET_NUM_CH; i++) {
302 get_sh_eth_mac(i + SH7757LCR_ETHERNET_NUM_CH, mac_string, buf);
303 sprintf(env_string, "eth%daddr", i + SH7757LCR_ETHERNET_NUM_CH);
304 env_set(env_string, mac_string);
306 set_mac_to_sh_giga_eth_register(i, mac_string);
312 static void init_pcie(void)
314 struct pcie_setup_regs *pcie_setup = PCIE_SETUP_BASE;
315 struct pcie_system_bus_regs *pcie_sysbus = PCIE_SYSTEM_BUS_BASE;
317 writel(0x00000ff2, &pcie_setup->ladmsk0);
318 writel(0x00000001, &pcie_setup->barmap);
319 writel(0xffcaa000, &pcie_setup->lad0);
320 writel(0x00030000, &pcie_sysbus->endictl0);
321 writel(0x00000003, &pcie_sysbus->endictl1);
322 writel(0x00000004, &pcie_setup->pbictl2);
325 static void finish_spiboot(void)
327 struct gctrl_regs *gctrl = GCTRL_BASE;
329 * SH7757 B0 does not use LBSC.
330 * So if we set SPIBOOTCAN to 1, SH7757 can not access Area0.
331 * This setting is not cleared by manual reset, So we have to set it
334 writel(0x00000000, &gctrl->spibootcan);
337 int board_late_init(void)
347 int do_sh_g200(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
349 struct gctrl_regs *gctrl = GCTRL_BASE;
350 unsigned long graofst;
352 writel(0xfedcba98, &gctrl->wprotect);
353 graofst = (SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_GRA_OFFSET) >> 24;
354 writel(graofst | 0xa0000f00, &gctrl->gracr3);
360 sh_g200, 1, 1, do_sh_g200,
362 "enable SH-G200 bus (disable PCIe-G200)"
365 #ifdef CONFIG_DEPRECATED
366 int do_write_mac(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
369 char mac_string[256];
370 struct spi_flash *spi;
376 printf("%s: malloc error.\n", __func__);
380 get_sh_eth_mac_raw(buf, 256);
382 /* print current MAC address */
383 for (i = 0; i < 4; i++) {
384 get_sh_eth_mac(i, mac_string, buf);
386 printf(" ETHERC ch%d = %s\n", i, mac_string);
388 printf("GETHERC ch%d = %s\n", i-2, mac_string);
395 memset(mac_string, 0xff, sizeof(mac_string));
396 sprintf(mac_string, "%s\t%s\t%s\t%s",
397 argv[1], argv[2], argv[3], argv[4]);
399 /* write MAC data to SPI rom */
400 spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);
402 printf("%s: spi_flash probe error.\n", __func__);
406 ret = spi_flash_erase(spi, SH7757LCR_ETHERNET_MAC_BASE_SPI,
407 SH7757LCR_SPI_SECTOR_SIZE);
409 printf("%s: spi_flash erase error.\n", __func__);
413 ret = spi_flash_write(spi, SH7757LCR_ETHERNET_MAC_BASE_SPI,
414 sizeof(mac_string), mac_string);
416 printf("%s: spi_flash write error.\n", __func__);
422 puts("The writing of the MAC address to SPI ROM was completed.\n");
428 write_mac, 5, 1, do_write_mac,
429 "write MAC address for ETHERC/GETHERC",
430 "[ETHERC ch0] [ETHERC ch1] [GETHERC ch0] [GETHERC ch1]\n"