2 * Copyright (C) 2012 Renesas Solutions Corp.
4 * SPDX-License-Identifier: GPL-2.0+
9 #include <asm/processor.h>
13 #include <spi_flash.h>
17 puts("BOARD: SH7753 EVB\n");
22 static void init_gpio(void)
24 struct gpio_regs *gpio = GPIO_BASE;
25 struct sermux_regs *sermux = SERMUX_BASE;
28 writew(0x0000, &gpio->pacr); /* GETHER */
29 writew(0x0001, &gpio->pbcr); /* INTC */
30 writew(0x0000, &gpio->pccr); /* PWMU, INTC */
31 writew(0x0000, &gpio->pdcr); /* SPI0 */
32 writew(0xeaff, &gpio->pecr); /* GPIO */
33 writew(0x0000, &gpio->pfcr); /* WDT */
34 writew(0x0004, &gpio->pgcr); /* SPI0, GETHER MDIO gate(PTG1) */
35 writew(0x0000, &gpio->phcr); /* SPI1 */
36 writew(0x0000, &gpio->picr); /* SDHI */
37 writew(0x0000, &gpio->pjcr); /* SCIF4 */
38 writew(0x0003, &gpio->pkcr); /* SerMux */
39 writew(0x0000, &gpio->plcr); /* SerMux */
40 writew(0x0000, &gpio->pmcr); /* RIIC */
41 writew(0x0000, &gpio->pncr); /* USB, SGPIO */
42 writew(0x0000, &gpio->pocr); /* SGPIO */
43 writew(0xd555, &gpio->pqcr); /* GPIO */
44 writew(0x0000, &gpio->prcr); /* RIIC */
45 writew(0x0000, &gpio->pscr); /* RIIC */
46 writew(0x0000, &gpio->ptcr); /* STATUS */
47 writeb(0x00, &gpio->pudr);
48 writew(0x5555, &gpio->pucr); /* Debug LED */
49 writew(0x0000, &gpio->pvcr); /* RSPI */
50 writew(0x0000, &gpio->pwcr); /* EVC */
51 writew(0x0000, &gpio->pxcr); /* LBSC */
52 writew(0x0000, &gpio->pycr); /* LBSC */
53 writew(0x0000, &gpio->pzcr); /* eMMC */
54 writew(0xfe00, &gpio->psel0);
55 writew(0x0000, &gpio->psel1);
56 writew(0x3000, &gpio->psel2);
57 writew(0xff00, &gpio->psel3);
58 writew(0x771f, &gpio->psel4);
59 writew(0x0ffc, &gpio->psel5);
60 writew(0x00ff, &gpio->psel6);
61 writew(0xfc00, &gpio->psel7);
63 writeb(0x10, &sermux->smr0); /* SMR0: SerMux mode 0 */
66 static void init_usb_phy(void)
68 struct usb_common_regs *common0 = USB0_COMMON_BASE;
69 struct usb_common_regs *common1 = USB1_COMMON_BASE;
70 struct usb0_phy_regs *phy = USB0_PHY_BASE;
71 struct usb1_port_regs *port = USB1_PORT_BASE;
72 struct usb1_alignment_regs *align = USB1_ALIGNMENT_BASE;
74 writew(0x0100, &phy->reset); /* set reset */
75 /* port0 = USB0, port1 = USB1 */
76 writew(0x0002, &phy->portsel);
77 writel(0x0001, &port->port1sel); /* port1 = Host */
78 writew(0x0111, &phy->reset); /* clear reset */
80 writew(0x4000, &common0->suspmode);
81 writew(0x4000, &common1->suspmode);
83 #if defined(__LITTLE_ENDIAN)
84 writel(0x00000000, &align->ehcidatac);
85 writel(0x00000000, &align->ohcidatac);
89 static void init_gether_mdio(void)
91 struct gpio_regs *gpio = GPIO_BASE;
93 writew(readw(&gpio->pgcr) | 0x0004, &gpio->pgcr);
94 writeb(readb(&gpio->pgdr) | 0x02, &gpio->pgdr); /* Use ET0-MDIO */
97 static void set_mac_to_sh_giga_eth_register(int channel, char *mac_string)
99 struct ether_mac_regs *ether;
100 unsigned char mac[6];
103 eth_parse_enetaddr(mac_string, mac);
106 ether = GETHER0_MAC_BASE;
108 ether = GETHER1_MAC_BASE;
110 val = (mac[0] << 24) | (mac[1] << 16) | (mac[2] << 8) | mac[3];
111 writel(val, ðer->mahr);
112 val = (mac[4] << 8) | mac[5];
113 writel(val, ðer->malr);
116 #if defined(CONFIG_SH_32BIT)
117 /*****************************************************************
118 * This PMB must be set on this timing. The lowlevel_init is run on
119 * Area 0(phys 0x00000000), so we have to map it.
121 * The new PMB table is following:
122 * ent virt phys v sz c wt
123 * 0 0xa0000000 0x40000000 1 128M 0 1
124 * 1 0xa8000000 0x48000000 1 128M 0 1
125 * 2 0xb0000000 0x50000000 1 128M 0 1
126 * 3 0xb8000000 0x58000000 1 128M 0 1
127 * 4 0x80000000 0x40000000 1 128M 1 1
128 * 5 0x88000000 0x48000000 1 128M 1 1
129 * 6 0x90000000 0x50000000 1 128M 1 1
130 * 7 0x98000000 0x58000000 1 128M 1 1
132 static void set_pmb_on_board_init(void)
134 struct mmu_regs *mmu = MMU_BASE;
137 writel(0x00000004, &mmu->mmucr);
139 /* delete PMB for SPIBOOT */
140 writel(0, PMB_ADDR_BASE(0));
141 writel(0, PMB_DATA_BASE(0));
143 /* add PMB for SDRAM(0x40000000 - 0x47ffffff) */
144 /* ppn ub v s1 s0 c wt */
145 writel(mk_pmb_addr_val(0xa0), PMB_ADDR_BASE(0));
146 writel(mk_pmb_data_val(0x40, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(0));
147 writel(mk_pmb_addr_val(0xb0), PMB_ADDR_BASE(2));
148 writel(mk_pmb_data_val(0x50, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(2));
149 writel(mk_pmb_addr_val(0xb8), PMB_ADDR_BASE(3));
150 writel(mk_pmb_data_val(0x58, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(3));
151 writel(mk_pmb_addr_val(0x80), PMB_ADDR_BASE(4));
152 writel(mk_pmb_data_val(0x40, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(4));
153 writel(mk_pmb_addr_val(0x90), PMB_ADDR_BASE(6));
154 writel(mk_pmb_data_val(0x50, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(6));
155 writel(mk_pmb_addr_val(0x98), PMB_ADDR_BASE(7));
156 writel(mk_pmb_data_val(0x58, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(7));
162 struct gether_control_regs *gether = GETHER_CONTROL_BASE;
165 #if defined(CONFIG_SH_32BIT)
166 set_pmb_on_board_init();
169 /* Sets TXnDLY to B'010 */
170 writel(0x00000202, &gether->gbecont);
180 DECLARE_GLOBAL_DATA_PTR;
182 gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
183 gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
184 printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
189 int board_mmc_init(bd_t *bis)
191 struct gpio_regs *gpio = GPIO_BASE;
193 writew(readw(&gpio->pgcr) | 0x0040, &gpio->pgcr);
194 writeb(readb(&gpio->pgdr) & ~0x08, &gpio->pgdr); /* Reset */
196 writeb(readb(&gpio->pgdr) | 0x08, &gpio->pgdr); /* Release reset */
199 return mmcif_mmc_init();
202 static int get_sh_eth_mac_raw(unsigned char *buf, int size)
204 struct spi_flash *spi;
207 spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);
209 printf("%s: spi_flash probe failed.\n", __func__);
213 ret = spi_flash_read(spi, SH7753EVB_ETHERNET_MAC_BASE, size, buf);
215 printf("%s: spi_flash read failed.\n", __func__);
224 static int get_sh_eth_mac(int channel, char *mac_string, unsigned char *buf)
226 memcpy(mac_string, &buf[channel * (SH7753EVB_ETHERNET_MAC_SIZE + 1)],
227 SH7753EVB_ETHERNET_MAC_SIZE);
228 mac_string[SH7753EVB_ETHERNET_MAC_SIZE] = 0x00; /* terminate */
233 static void init_ethernet_mac(void)
242 printf("%s: malloc failed.\n", __func__);
245 get_sh_eth_mac_raw(buf, 256);
247 /* Gigabit Ethernet */
248 for (i = 0; i < SH7753EVB_ETHERNET_NUM_CH; i++) {
249 get_sh_eth_mac(i, mac_string, buf);
251 setenv("ethaddr", mac_string);
253 sprintf(env_string, "eth%daddr", i);
254 setenv(env_string, mac_string);
256 set_mac_to_sh_giga_eth_register(i, mac_string);
262 int board_late_init(void)
269 int do_write_mac(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
272 char mac_string[256];
273 struct spi_flash *spi;
279 printf("%s: malloc failed.\n", __func__);
283 get_sh_eth_mac_raw(buf, 256);
285 /* print current MAC address */
286 for (i = 0; i < SH7753EVB_ETHERNET_NUM_CH; i++) {
287 get_sh_eth_mac(i, mac_string, buf);
288 printf("GETHERC ch%d = %s\n", i, mac_string);
295 memset(mac_string, 0xff, sizeof(mac_string));
296 sprintf(mac_string, "%s\t%s",
299 /* write MAC data to SPI rom */
300 spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);
302 printf("%s: spi_flash probe failed.\n", __func__);
306 ret = spi_flash_erase(spi, SH7753EVB_ETHERNET_MAC_BASE_SPI,
307 SH7753EVB_SPI_SECTOR_SIZE);
309 printf("%s: spi_flash erase failed.\n", __func__);
313 ret = spi_flash_write(spi, SH7753EVB_ETHERNET_MAC_BASE_SPI,
314 sizeof(mac_string), mac_string);
316 printf("%s: spi_flash write failed.\n", __func__);
322 puts("The writing of the MAC address to SPI ROM was completed.\n");
328 write_mac, 3, 1, do_write_mac,
329 "write MAC address for GETHERC",
330 "[GETHERC ch0] [GETHERC ch1]\n"