2 * Copyright (C) 2013 Renesas Solutions Corp.
4 * SPDX-License-Identifier: GPL-2.0+
8 #include <asm/processor.h>
11 .macro or32, addr, data
25 .section .spiboot1.text
40 /* If CPU runs on SDRAM (PC=0x5???????) or not. */
41 PC_MASK: .long 0x20000000
48 mov.l EXPEVT_POWER_ON_RESET, r1
53 * If EXPEVT value is manual reset or tlb multipul-hit,
54 * initialization of DBSC3 is not necessary.
60 /*------- Reset -------*/
61 write32 MRSTCR0_A, MRSTCR0_D
62 write32 MRSTCR1_A, MRSTCR1_D
71 * If DBACEN == 1(DBSC was already enabled), we have to avoid the
72 * initialization of DDR3-SDRAM.
78 /*------- DBSC3 -------*/
79 /* oscillation stabilization time */
80 wait_timer WAIT_OSC_TIME
83 write32 DBKIND_A, DBKIND_D
86 write32 DBCONF_A, DBCONF_D
87 write32 DBTR0_A, DBTR0_D
88 write32 DBTR1_A, DBTR1_D
89 write32 DBTR2_A, DBTR2_D
90 write32 DBTR3_A, DBTR3_D
91 write32 DBTR4_A, DBTR4_D
92 write32 DBTR5_A, DBTR5_D
93 write32 DBTR6_A, DBTR6_D
94 write32 DBTR7_A, DBTR7_D
95 write32 DBTR8_A, DBTR8_D
96 write32 DBTR9_A, DBTR9_D
97 write32 DBTR10_A, DBTR10_D
98 write32 DBTR11_A, DBTR11_D
99 write32 DBTR12_A, DBTR12_D
100 write32 DBTR13_A, DBTR13_D
101 write32 DBTR14_A, DBTR14_D
102 write32 DBTR15_A, DBTR15_D
103 write32 DBTR16_A, DBTR16_D
104 write32 DBTR17_A, DBTR17_D
105 write32 DBTR18_A, DBTR18_D
106 write32 DBTR19_A, DBTR19_D
107 write32 DBRNK0_A, DBRNK0_D
108 write32 DBADJ0_A, DBADJ0_D
109 write32 DBADJ2_A, DBADJ2_D
112 write32 DBCMD_A, DBCMD_RSTL_VAL
116 write32 DBCMD_A, DBCMD_PDEN_VAL
119 write32 DBPDCNT3_A, DBPDCNT3_D
122 write32 DBPDCNT1_A, DBPDCNT1_D
123 write32 DBPDCNT2_A, DBPDCNT2_D
124 write32 DBPDLCK_A, DBPDLCK_D
125 write32 DBPDRGA_A, DBPDRGA_D
126 write32 DBPDRGD_A, DBPDRGD_D
132 write32 DBPDCNT0_A, DBPDCNT0_D
139 write32 DBCMD_A, DBCMD_WAIT_VAL
143 write32 DBCMD_A, DBCMD_RSTH_VAL
147 write32 DBCMD_A, DBCMD_WAIT_VAL
148 write32 DBCMD_A, DBCMD_WAIT_VAL
149 write32 DBCMD_A, DBCMD_WAIT_VAL
150 write32 DBCMD_A, DBCMD_WAIT_VAL
153 write32 DBCMD_A, DBCMD_PDXT_VAL
156 write32 DBCMD_A, DBCMD_MRS2_VAL
159 write32 DBCMD_A, DBCMD_MRS3_VAL
162 write32 DBCMD_A, DBCMD_MRS1_VAL
165 write32 DBCMD_A, DBCMD_MRS0_VAL
166 write32 DBPDNCNF_A, DBPDNCNF_D
169 write32 DBCMD_A, DBCMD_ZQCL_VAL
171 write32 DBCMD_A, DBCMD_REF_VAL
172 write32 DBCMD_A, DBCMD_REF_VAL
176 write32 DBCALTR_A, DBCALTR_D
179 write32 DBRFCNF0_A, DBRFCNF0_D
180 write32 DBRFCNF1_A, DBRFCNF1_D
181 write32 DBRFCNF2_A, DBRFCNF2_D
184 write32 DBCALCNF_A, DBCALCNF_D
187 write32 DBRFEN_A, DBRFEN_D
188 write32 DBCMD_A, DBCMD_SRXT_VAL
191 write32 DBACEN_A, DBACEN_D
201 EXPEVT_A: .long 0xff000024
202 EXPEVT_POWER_ON_RESET: .long 0x00000000
204 /*------- Reset -------*/
205 MRSTCR0_A: .long 0xffd50030
206 MRSTCR0_D: .long 0xfe1ffe7f
207 MRSTCR1_A: .long 0xffd50034
208 MRSTCR1_D: .long 0xfff3ffff
210 /*------- DBSC3 -------*/
211 DBCMD_A: .long 0xfe800018
212 DBKIND_A: .long 0xfe800020
213 DBCONF_A: .long 0xfe800024
214 DBTR0_A: .long 0xfe800040
215 DBTR1_A: .long 0xfe800044
216 DBTR2_A: .long 0xfe800048
217 DBTR3_A: .long 0xfe800050
218 DBTR4_A: .long 0xfe800054
219 DBTR5_A: .long 0xfe800058
220 DBTR6_A: .long 0xfe80005c
221 DBTR7_A: .long 0xfe800060
222 DBTR8_A: .long 0xfe800064
223 DBTR9_A: .long 0xfe800068
224 DBTR10_A: .long 0xfe80006c
225 DBTR11_A: .long 0xfe800070
226 DBTR12_A: .long 0xfe800074
227 DBTR13_A: .long 0xfe800078
228 DBTR14_A: .long 0xfe80007c
229 DBTR15_A: .long 0xfe800080
230 DBTR16_A: .long 0xfe800084
231 DBTR17_A: .long 0xfe800088
232 DBTR18_A: .long 0xfe80008c
233 DBTR19_A: .long 0xfe800090
234 DBRNK0_A: .long 0xfe800100
235 DBPDCNT0_A: .long 0xfe800200
236 DBPDCNT1_A: .long 0xfe800204
237 DBPDCNT2_A: .long 0xfe800208
238 DBPDCNT3_A: .long 0xfe80020c
239 DBPDLCK_A: .long 0xfe800280
240 DBPDRGA_A: .long 0xfe800290
241 DBPDRGD_A: .long 0xfe8002a0
242 DBADJ0_A: .long 0xfe8000c0
243 DBADJ2_A: .long 0xfe8000c8
244 DBRFCNF0_A: .long 0xfe8000e0
245 DBRFCNF1_A: .long 0xfe8000e4
246 DBRFCNF2_A: .long 0xfe8000e8
247 DBCALCNF_A: .long 0xfe8000f4
248 DBRFEN_A: .long 0xfe800014
249 DBACEN_A: .long 0xfe800010
250 DBWAIT_A: .long 0xfe80001c
251 DBCALTR_A: .long 0xfe8000f8
252 DBPDNCNF_A: .long 0xfe800180
254 WAIT_OSC_TIME: .long 6000
255 WAIT_30US: .long 13333
257 DBCMD_RSTL_VAL: .long 0x20000000
258 DBCMD_PDEN_VAL: .long 0x1000d73c
259 DBCMD_WAIT_VAL: .long 0x0000d73c
260 DBCMD_RSTH_VAL: .long 0x2100d73c
261 DBCMD_PDXT_VAL: .long 0x110000c8
262 DBCMD_MRS0_VAL: .long 0x28000930
263 DBCMD_MRS1_VAL: .long 0x29000004
264 DBCMD_MRS2_VAL: .long 0x2a000008
265 DBCMD_MRS3_VAL: .long 0x2b000000
266 DBCMD_ZQCL_VAL: .long 0x03000200
267 DBCMD_REF_VAL: .long 0x0c000000
268 DBCMD_SRXT_VAL: .long 0x19000000
269 DBKIND_D: .long 0x00000007
270 DBCONF_D: .long 0x0f030a01
271 DBTR0_D: .long 0x00000007
272 DBTR1_D: .long 0x00000006
273 DBTR2_D: .long 0x00000000
274 DBTR3_D: .long 0x00000007
275 DBTR4_D: .long 0x00070007
276 DBTR5_D: .long 0x0000001b
277 DBTR6_D: .long 0x00000014
278 DBTR7_D: .long 0x00000004
279 DBTR8_D: .long 0x00000014
280 DBTR9_D: .long 0x00000004
281 DBTR10_D: .long 0x00000008
282 DBTR11_D: .long 0x00000007
283 DBTR12_D: .long 0x0000000e
284 DBTR13_D: .long 0x000000a0
285 DBTR14_D: .long 0x00060006
286 DBTR15_D: .long 0x00000003
287 DBTR16_D: .long 0x00160002
288 DBTR17_D: .long 0x000c0000
289 DBTR18_D: .long 0x00000200
290 DBTR19_D: .long 0x00000040
291 DBRNK0_D: .long 0x00000001
292 DBPDCNT0_D: .long 0x00000001
293 DBPDCNT1_D: .long 0x00000001
294 DBPDCNT2_D: .long 0x00000000
295 DBPDCNT3_D: .long 0x00004010
296 DBPDLCK_D: .long 0x0000a55a
297 DBPDRGA_D: .long 0x00000028
298 DBPDRGD_D: .long 0x00017100
300 DBADJ0_D: .long 0x00010000
301 DBADJ2_D: .long 0x18061806
302 DBRFCNF0_D: .long 0x000001ff
303 DBRFCNF1_D: .long 0x00081040
304 DBRFCNF2_D: .long 0x00000000
305 DBCALCNF_D: .long 0x0000ffff
306 DBRFEN_D: .long 0x00000001
307 DBACEN_D: .long 0x00000001
308 DBCALTR_D: .long 0x08200820
309 DBPDNCNF_D: .long 0x00000001
313 #if defined(CONFIG_SH_32BIT)
314 /*------- set PMB -------*/
315 write32 PASCR_A, PASCR_29BIT_D
316 write32 MMUCR_A, MMUCR_D
318 /*****************************************************************
319 * ent virt phys v sz c wt
320 * 0 0xa0000000 0x00000000 1 128M 0 1
321 * 1 0xa8000000 0x48000000 1 128M 0 1
322 * 5 0x88000000 0x48000000 1 128M 1 1
324 write32 PMB_ADDR_SPIBOOT_A, PMB_ADDR_SPIBOOT_D
325 write32 PMB_DATA_SPIBOOT_A, PMB_DATA_SPIBOOT_D
326 write32 PMB_ADDR_DDR_C1_A, PMB_ADDR_DDR_C1_D
327 write32 PMB_DATA_DDR_C1_A, PMB_DATA_DDR_C1_D
328 write32 PMB_ADDR_DDR_N1_A, PMB_ADDR_DDR_N1_D
329 write32 PMB_DATA_DDR_N1_A, PMB_DATA_DDR_N1_D
331 write32 PMB_ADDR_ENTRY2, PMB_ADDR_NOT_USE_D
332 write32 PMB_ADDR_ENTRY3, PMB_ADDR_NOT_USE_D
333 write32 PMB_ADDR_ENTRY4, PMB_ADDR_NOT_USE_D
334 write32 PMB_ADDR_ENTRY6, PMB_ADDR_NOT_USE_D
335 write32 PMB_ADDR_ENTRY7, PMB_ADDR_NOT_USE_D
336 write32 PMB_ADDR_ENTRY8, PMB_ADDR_NOT_USE_D
337 write32 PMB_ADDR_ENTRY9, PMB_ADDR_NOT_USE_D
338 write32 PMB_ADDR_ENTRY10, PMB_ADDR_NOT_USE_D
339 write32 PMB_ADDR_ENTRY11, PMB_ADDR_NOT_USE_D
340 write32 PMB_ADDR_ENTRY12, PMB_ADDR_NOT_USE_D
341 write32 PMB_ADDR_ENTRY13, PMB_ADDR_NOT_USE_D
342 write32 PMB_ADDR_ENTRY14, PMB_ADDR_NOT_USE_D
343 write32 PMB_ADDR_ENTRY15, PMB_ADDR_NOT_USE_D
345 write32 PASCR_A, PASCR_INIT
348 #endif /* if defined(CONFIG_SH_32BIT) */
351 /* CPU is running on ILRAM? */
356 mov.l _stack_ilram, r15
357 mov.l _spiboot_main, r0
362 _spiboot_main: .long (spiboot_main - (100b + 4))
363 _stack_ilram: .long 0xe5204000
373 #if defined(CONFIG_SH_32BIT)
374 /*------- set PMB -------*/
375 PMB_ADDR_SPIBOOT_A: .long PMB_ADDR_BASE(0)
376 PMB_ADDR_DDR_N1_A: .long PMB_ADDR_BASE(1)
377 PMB_ADDR_DDR_C1_A: .long PMB_ADDR_BASE(5)
378 PMB_ADDR_ENTRY2: .long PMB_ADDR_BASE(2)
379 PMB_ADDR_ENTRY3: .long PMB_ADDR_BASE(3)
380 PMB_ADDR_ENTRY4: .long PMB_ADDR_BASE(4)
381 PMB_ADDR_ENTRY6: .long PMB_ADDR_BASE(6)
382 PMB_ADDR_ENTRY7: .long PMB_ADDR_BASE(7)
383 PMB_ADDR_ENTRY8: .long PMB_ADDR_BASE(8)
384 PMB_ADDR_ENTRY9: .long PMB_ADDR_BASE(9)
385 PMB_ADDR_ENTRY10: .long PMB_ADDR_BASE(10)
386 PMB_ADDR_ENTRY11: .long PMB_ADDR_BASE(11)
387 PMB_ADDR_ENTRY12: .long PMB_ADDR_BASE(12)
388 PMB_ADDR_ENTRY13: .long PMB_ADDR_BASE(13)
389 PMB_ADDR_ENTRY14: .long PMB_ADDR_BASE(14)
390 PMB_ADDR_ENTRY15: .long PMB_ADDR_BASE(15)
392 PMB_ADDR_SPIBOOT_D: .long mk_pmb_addr_val(0xa0)
393 PMB_ADDR_DDR_C1_D: .long mk_pmb_addr_val(0x88)
394 PMB_ADDR_DDR_N1_D: .long mk_pmb_addr_val(0xa8)
395 PMB_ADDR_NOT_USE_D: .long 0x00000000
397 PMB_DATA_SPIBOOT_A: .long PMB_DATA_BASE(0)
398 PMB_DATA_DDR_N1_A: .long PMB_DATA_BASE(1)
399 PMB_DATA_DDR_C1_A: .long PMB_DATA_BASE(5)
401 /* ppn ub v s1 s0 c wt */
402 PMB_DATA_SPIBOOT_D: .long mk_pmb_data_val(0x00, 0, 1, 1, 0, 0, 1)
403 PMB_DATA_DDR_C1_D: .long mk_pmb_data_val(0x48, 0, 1, 1, 0, 1, 1)
404 PMB_DATA_DDR_N1_D: .long mk_pmb_data_val(0x48, 1, 1, 1, 0, 0, 1)
406 PASCR_A: .long 0xff000070
407 DUMMY_ADDR: .long 0xa0000000
408 PASCR_29BIT_D: .long 0x00000000
409 PASCR_INIT: .long 0x80000080
410 MMUCR_A: .long 0xff000010
411 MMUCR_D: .long 0x00000004 /* clear ITLB */
412 #endif /* CONFIG_SH_32BIT */
415 CCR_D: .long CCR_CACHE_INIT