1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2013 Renesas Solutions Corp.
7 #include <asm/processor.h>
10 .macro or32, addr, data
24 .section .spiboot1.text
39 /* If CPU runs on SDRAM (PC=0x5???????) or not. */
40 PC_MASK: .long 0x20000000
47 mov.l EXPEVT_POWER_ON_RESET, r1
52 * If EXPEVT value is manual reset or tlb multipul-hit,
53 * initialization of DBSC3 is not necessary.
59 /*------- Reset -------*/
60 write32 MRSTCR0_A, MRSTCR0_D
61 write32 MRSTCR1_A, MRSTCR1_D
70 * If DBACEN == 1(DBSC was already enabled), we have to avoid the
71 * initialization of DDR3-SDRAM.
77 /*------- DBSC3 -------*/
78 /* oscillation stabilization time */
79 wait_timer WAIT_OSC_TIME
82 write32 DBKIND_A, DBKIND_D
85 write32 DBCONF_A, DBCONF_D
86 write32 DBTR0_A, DBTR0_D
87 write32 DBTR1_A, DBTR1_D
88 write32 DBTR2_A, DBTR2_D
89 write32 DBTR3_A, DBTR3_D
90 write32 DBTR4_A, DBTR4_D
91 write32 DBTR5_A, DBTR5_D
92 write32 DBTR6_A, DBTR6_D
93 write32 DBTR7_A, DBTR7_D
94 write32 DBTR8_A, DBTR8_D
95 write32 DBTR9_A, DBTR9_D
96 write32 DBTR10_A, DBTR10_D
97 write32 DBTR11_A, DBTR11_D
98 write32 DBTR12_A, DBTR12_D
99 write32 DBTR13_A, DBTR13_D
100 write32 DBTR14_A, DBTR14_D
101 write32 DBTR15_A, DBTR15_D
102 write32 DBTR16_A, DBTR16_D
103 write32 DBTR17_A, DBTR17_D
104 write32 DBTR18_A, DBTR18_D
105 write32 DBTR19_A, DBTR19_D
106 write32 DBRNK0_A, DBRNK0_D
107 write32 DBADJ0_A, DBADJ0_D
108 write32 DBADJ2_A, DBADJ2_D
111 write32 DBCMD_A, DBCMD_RSTL_VAL
115 write32 DBCMD_A, DBCMD_PDEN_VAL
118 write32 DBPDCNT3_A, DBPDCNT3_D
121 write32 DBPDCNT1_A, DBPDCNT1_D
122 write32 DBPDCNT2_A, DBPDCNT2_D
123 write32 DBPDLCK_A, DBPDLCK_D
124 write32 DBPDRGA_A, DBPDRGA_D
125 write32 DBPDRGD_A, DBPDRGD_D
131 write32 DBPDCNT0_A, DBPDCNT0_D
138 write32 DBCMD_A, DBCMD_WAIT_VAL
142 write32 DBCMD_A, DBCMD_RSTH_VAL
146 write32 DBCMD_A, DBCMD_WAIT_VAL
147 write32 DBCMD_A, DBCMD_WAIT_VAL
148 write32 DBCMD_A, DBCMD_WAIT_VAL
149 write32 DBCMD_A, DBCMD_WAIT_VAL
152 write32 DBCMD_A, DBCMD_PDXT_VAL
155 write32 DBCMD_A, DBCMD_MRS2_VAL
158 write32 DBCMD_A, DBCMD_MRS3_VAL
161 write32 DBCMD_A, DBCMD_MRS1_VAL
164 write32 DBCMD_A, DBCMD_MRS0_VAL
165 write32 DBPDNCNF_A, DBPDNCNF_D
168 write32 DBCMD_A, DBCMD_ZQCL_VAL
170 write32 DBCMD_A, DBCMD_REF_VAL
171 write32 DBCMD_A, DBCMD_REF_VAL
175 write32 DBCALTR_A, DBCALTR_D
178 write32 DBRFCNF0_A, DBRFCNF0_D
179 write32 DBRFCNF1_A, DBRFCNF1_D
180 write32 DBRFCNF2_A, DBRFCNF2_D
183 write32 DBCALCNF_A, DBCALCNF_D
186 write32 DBRFEN_A, DBRFEN_D
187 write32 DBCMD_A, DBCMD_SRXT_VAL
190 write32 DBACEN_A, DBACEN_D
200 EXPEVT_A: .long 0xff000024
201 EXPEVT_POWER_ON_RESET: .long 0x00000000
203 /*------- Reset -------*/
204 MRSTCR0_A: .long 0xffd50030
205 MRSTCR0_D: .long 0xfe1ffe7f
206 MRSTCR1_A: .long 0xffd50034
207 MRSTCR1_D: .long 0xfff3ffff
209 /*------- DBSC3 -------*/
210 DBCMD_A: .long 0xfe800018
211 DBKIND_A: .long 0xfe800020
212 DBCONF_A: .long 0xfe800024
213 DBTR0_A: .long 0xfe800040
214 DBTR1_A: .long 0xfe800044
215 DBTR2_A: .long 0xfe800048
216 DBTR3_A: .long 0xfe800050
217 DBTR4_A: .long 0xfe800054
218 DBTR5_A: .long 0xfe800058
219 DBTR6_A: .long 0xfe80005c
220 DBTR7_A: .long 0xfe800060
221 DBTR8_A: .long 0xfe800064
222 DBTR9_A: .long 0xfe800068
223 DBTR10_A: .long 0xfe80006c
224 DBTR11_A: .long 0xfe800070
225 DBTR12_A: .long 0xfe800074
226 DBTR13_A: .long 0xfe800078
227 DBTR14_A: .long 0xfe80007c
228 DBTR15_A: .long 0xfe800080
229 DBTR16_A: .long 0xfe800084
230 DBTR17_A: .long 0xfe800088
231 DBTR18_A: .long 0xfe80008c
232 DBTR19_A: .long 0xfe800090
233 DBRNK0_A: .long 0xfe800100
234 DBPDCNT0_A: .long 0xfe800200
235 DBPDCNT1_A: .long 0xfe800204
236 DBPDCNT2_A: .long 0xfe800208
237 DBPDCNT3_A: .long 0xfe80020c
238 DBPDLCK_A: .long 0xfe800280
239 DBPDRGA_A: .long 0xfe800290
240 DBPDRGD_A: .long 0xfe8002a0
241 DBADJ0_A: .long 0xfe8000c0
242 DBADJ2_A: .long 0xfe8000c8
243 DBRFCNF0_A: .long 0xfe8000e0
244 DBRFCNF1_A: .long 0xfe8000e4
245 DBRFCNF2_A: .long 0xfe8000e8
246 DBCALCNF_A: .long 0xfe8000f4
247 DBRFEN_A: .long 0xfe800014
248 DBACEN_A: .long 0xfe800010
249 DBWAIT_A: .long 0xfe80001c
250 DBCALTR_A: .long 0xfe8000f8
251 DBPDNCNF_A: .long 0xfe800180
253 WAIT_OSC_TIME: .long 6000
254 WAIT_30US: .long 13333
256 DBCMD_RSTL_VAL: .long 0x20000000
257 DBCMD_PDEN_VAL: .long 0x1000d73c
258 DBCMD_WAIT_VAL: .long 0x0000d73c
259 DBCMD_RSTH_VAL: .long 0x2100d73c
260 DBCMD_PDXT_VAL: .long 0x110000c8
261 DBCMD_MRS0_VAL: .long 0x28000930
262 DBCMD_MRS1_VAL: .long 0x29000004
263 DBCMD_MRS2_VAL: .long 0x2a000008
264 DBCMD_MRS3_VAL: .long 0x2b000000
265 DBCMD_ZQCL_VAL: .long 0x03000200
266 DBCMD_REF_VAL: .long 0x0c000000
267 DBCMD_SRXT_VAL: .long 0x19000000
268 DBKIND_D: .long 0x00000007
269 DBCONF_D: .long 0x0f030a01
270 DBTR0_D: .long 0x00000007
271 DBTR1_D: .long 0x00000006
272 DBTR2_D: .long 0x00000000
273 DBTR3_D: .long 0x00000007
274 DBTR4_D: .long 0x00070007
275 DBTR5_D: .long 0x0000001b
276 DBTR6_D: .long 0x00000014
277 DBTR7_D: .long 0x00000004
278 DBTR8_D: .long 0x00000014
279 DBTR9_D: .long 0x00000004
280 DBTR10_D: .long 0x00000008
281 DBTR11_D: .long 0x00000007
282 DBTR12_D: .long 0x0000000e
283 DBTR13_D: .long 0x000000a0
284 DBTR14_D: .long 0x00060006
285 DBTR15_D: .long 0x00000003
286 DBTR16_D: .long 0x00160002
287 DBTR17_D: .long 0x000c0000
288 DBTR18_D: .long 0x00000200
289 DBTR19_D: .long 0x00000040
290 DBRNK0_D: .long 0x00000001
291 DBPDCNT0_D: .long 0x00000001
292 DBPDCNT1_D: .long 0x00000001
293 DBPDCNT2_D: .long 0x00000000
294 DBPDCNT3_D: .long 0x00004010
295 DBPDLCK_D: .long 0x0000a55a
296 DBPDRGA_D: .long 0x00000028
297 DBPDRGD_D: .long 0x00017100
299 DBADJ0_D: .long 0x00010000
300 DBADJ2_D: .long 0x18061806
301 DBRFCNF0_D: .long 0x000001ff
302 DBRFCNF1_D: .long 0x00081040
303 DBRFCNF2_D: .long 0x00000000
304 DBCALCNF_D: .long 0x0000ffff
305 DBRFEN_D: .long 0x00000001
306 DBACEN_D: .long 0x00000001
307 DBCALTR_D: .long 0x08200820
308 DBPDNCNF_D: .long 0x00000001
312 #if defined(CONFIG_SH_32BIT)
313 /*------- set PMB -------*/
314 write32 PASCR_A, PASCR_29BIT_D
315 write32 MMUCR_A, MMUCR_D
317 /*****************************************************************
318 * ent virt phys v sz c wt
319 * 0 0xa0000000 0x00000000 1 128M 0 1
320 * 1 0xa8000000 0x48000000 1 128M 0 1
321 * 5 0x88000000 0x48000000 1 128M 1 1
323 write32 PMB_ADDR_SPIBOOT_A, PMB_ADDR_SPIBOOT_D
324 write32 PMB_DATA_SPIBOOT_A, PMB_DATA_SPIBOOT_D
325 write32 PMB_ADDR_DDR_C1_A, PMB_ADDR_DDR_C1_D
326 write32 PMB_DATA_DDR_C1_A, PMB_DATA_DDR_C1_D
327 write32 PMB_ADDR_DDR_N1_A, PMB_ADDR_DDR_N1_D
328 write32 PMB_DATA_DDR_N1_A, PMB_DATA_DDR_N1_D
330 write32 PMB_ADDR_ENTRY2, PMB_ADDR_NOT_USE_D
331 write32 PMB_ADDR_ENTRY3, PMB_ADDR_NOT_USE_D
332 write32 PMB_ADDR_ENTRY4, PMB_ADDR_NOT_USE_D
333 write32 PMB_ADDR_ENTRY6, PMB_ADDR_NOT_USE_D
334 write32 PMB_ADDR_ENTRY7, PMB_ADDR_NOT_USE_D
335 write32 PMB_ADDR_ENTRY8, PMB_ADDR_NOT_USE_D
336 write32 PMB_ADDR_ENTRY9, PMB_ADDR_NOT_USE_D
337 write32 PMB_ADDR_ENTRY10, PMB_ADDR_NOT_USE_D
338 write32 PMB_ADDR_ENTRY11, PMB_ADDR_NOT_USE_D
339 write32 PMB_ADDR_ENTRY12, PMB_ADDR_NOT_USE_D
340 write32 PMB_ADDR_ENTRY13, PMB_ADDR_NOT_USE_D
341 write32 PMB_ADDR_ENTRY14, PMB_ADDR_NOT_USE_D
342 write32 PMB_ADDR_ENTRY15, PMB_ADDR_NOT_USE_D
344 write32 PASCR_A, PASCR_INIT
347 #endif /* if defined(CONFIG_SH_32BIT) */
350 /* CPU is running on ILRAM? */
355 mov.l _stack_ilram, r15
356 mov.l _spiboot_main, r0
361 _spiboot_main: .long (spiboot_main - (100b + 4))
362 _stack_ilram: .long 0xe5204000
372 #if defined(CONFIG_SH_32BIT)
373 /*------- set PMB -------*/
374 PMB_ADDR_SPIBOOT_A: .long PMB_ADDR_BASE(0)
375 PMB_ADDR_DDR_N1_A: .long PMB_ADDR_BASE(1)
376 PMB_ADDR_DDR_C1_A: .long PMB_ADDR_BASE(5)
377 PMB_ADDR_ENTRY2: .long PMB_ADDR_BASE(2)
378 PMB_ADDR_ENTRY3: .long PMB_ADDR_BASE(3)
379 PMB_ADDR_ENTRY4: .long PMB_ADDR_BASE(4)
380 PMB_ADDR_ENTRY6: .long PMB_ADDR_BASE(6)
381 PMB_ADDR_ENTRY7: .long PMB_ADDR_BASE(7)
382 PMB_ADDR_ENTRY8: .long PMB_ADDR_BASE(8)
383 PMB_ADDR_ENTRY9: .long PMB_ADDR_BASE(9)
384 PMB_ADDR_ENTRY10: .long PMB_ADDR_BASE(10)
385 PMB_ADDR_ENTRY11: .long PMB_ADDR_BASE(11)
386 PMB_ADDR_ENTRY12: .long PMB_ADDR_BASE(12)
387 PMB_ADDR_ENTRY13: .long PMB_ADDR_BASE(13)
388 PMB_ADDR_ENTRY14: .long PMB_ADDR_BASE(14)
389 PMB_ADDR_ENTRY15: .long PMB_ADDR_BASE(15)
391 PMB_ADDR_SPIBOOT_D: .long mk_pmb_addr_val(0xa0)
392 PMB_ADDR_DDR_C1_D: .long mk_pmb_addr_val(0x88)
393 PMB_ADDR_DDR_N1_D: .long mk_pmb_addr_val(0xa8)
394 PMB_ADDR_NOT_USE_D: .long 0x00000000
396 PMB_DATA_SPIBOOT_A: .long PMB_DATA_BASE(0)
397 PMB_DATA_DDR_N1_A: .long PMB_DATA_BASE(1)
398 PMB_DATA_DDR_C1_A: .long PMB_DATA_BASE(5)
400 /* ppn ub v s1 s0 c wt */
401 PMB_DATA_SPIBOOT_D: .long mk_pmb_data_val(0x00, 0, 1, 1, 0, 0, 1)
402 PMB_DATA_DDR_C1_D: .long mk_pmb_data_val(0x48, 0, 1, 1, 0, 1, 1)
403 PMB_DATA_DDR_N1_D: .long mk_pmb_data_val(0x48, 1, 1, 1, 0, 0, 1)
405 PASCR_A: .long 0xff000070
406 DUMMY_ADDR: .long 0xa0000000
407 PASCR_29BIT_D: .long 0x00000000
408 PASCR_INIT: .long 0x80000080
409 MMUCR_A: .long 0xff000010
410 MMUCR_D: .long 0x00000004 /* clear ITLB */
411 #endif /* CONFIG_SH_32BIT */
414 CCR_D: .long CCR_CACHE_INIT