1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2012 Renesas Solutions Corp.
7 #include <asm/processor.h>
10 .macro or32, addr, data
24 .section .spiboot1.text
28 /*------- GPIO -------*/
29 write16 PDCR_A, PDCR_D ! SPI0
30 write16 PGCR_A, PGCR_D ! SPI0, GETHER MDIO gate(PTG1)
31 write16 PJCR_A, PJCR_D ! SCIF4
32 write16 PTCR_A, PTCR_D ! STATUS
33 write16 PSEL1_A, PSEL1_D ! SPI0
34 write16 PSEL2_A, PSEL2_D ! SPI0
35 write16 PSEL5_A, PSEL5_D ! STATUS
42 /*------- GPIO -------*/
43 PDCR_A: .long 0xffec0006
44 PGCR_A: .long 0xffec000c
45 PJCR_A: .long 0xffec0012
46 PTCR_A: .long 0xffec0026
47 PSEL1_A: .long 0xffec0072
48 PSEL2_A: .long 0xffec0074
49 PSEL5_A: .long 0xffec007a
73 /* If CPU runs on SDRAM (PC=0x5???????) or not. */
74 PC_MASK: .long 0x20000000
81 mov.l EXPEVT_POWER_ON_RESET, r1
86 * If EXPEVT value is manual reset or tlb multipul-hit,
87 * initialization of DDR3IF is not necessary.
93 /*------- Reset -------*/
94 write32 MRSTCR0_A, MRSTCR0_D
95 write32 MRSTCR1_A, MRSTCR1_D
104 * If DBACEN == 1(DBSC was already enabled), we have to avoid the
105 * initialization of DDR3-SDRAM.
111 /*------- DDR3IF -------*/
112 /* oscillation stabilization time */
113 wait_timer WAIT_OSC_TIME
116 write32 DBCMD_A, DBCMD_RSTL_VAL
120 write32 DBCMD_A, DBCMD_PDEN_VAL
123 write32 DBKIND_A, DBKIND_D
126 write32 DBCONF_A, DBCONF_D
127 write32 DBTR0_A, DBTR0_D
128 write32 DBTR1_A, DBTR1_D
129 write32 DBTR2_A, DBTR2_D
130 write32 DBTR3_A, DBTR3_D
131 write32 DBTR4_A, DBTR4_D
132 write32 DBTR5_A, DBTR5_D
133 write32 DBTR6_A, DBTR6_D
134 write32 DBTR7_A, DBTR7_D
135 write32 DBTR8_A, DBTR8_D
136 write32 DBTR9_A, DBTR9_D
137 write32 DBTR10_A, DBTR10_D
138 write32 DBTR11_A, DBTR11_D
139 write32 DBTR12_A, DBTR12_D
140 write32 DBTR13_A, DBTR13_D
141 write32 DBTR14_A, DBTR14_D
142 write32 DBTR15_A, DBTR15_D
143 write32 DBTR16_A, DBTR16_D
144 write32 DBTR17_A, DBTR17_D
145 write32 DBTR18_A, DBTR18_D
146 write32 DBTR19_A, DBTR19_D
147 write32 DBRNK0_A, DBRNK0_D
150 write32 DBPDCNT3_A, DBPDCNT3_D
153 write32 DBPDCNT1_A, DBPDCNT1_D
154 write32 DBPDCNT2_A, DBPDCNT2_D
155 write32 DBPDLCK_A, DBPDLCK_D
156 write32 DBPDRGA_A, DBPDRGA_D
157 write32 DBPDRGD_A, DBPDRGD_D
163 write32 DBPDCNT0_A, DBPDCNT0_D
170 write32 DBCMD_A, DBCMD_WAIT_VAL
174 write32 DBCMD_A, DBCMD_RSTH_VAL
178 write32 DBCMD_A, DBCMD_WAIT_VAL
179 write32 DBCMD_A, DBCMD_WAIT_VAL
180 write32 DBCMD_A, DBCMD_WAIT_VAL
181 write32 DBCMD_A, DBCMD_WAIT_VAL
184 write32 DBCMD_A, DBCMD_PDXT_VAL
187 write32 DBCMD_A, DBCMD_MRS2_VAL
190 write32 DBCMD_A, DBCMD_MRS3_VAL
193 write32 DBCMD_A, DBCMD_MRS1_VAL
196 write32 DBCMD_A, DBCMD_MRS0_VAL
199 write32 DBCMD_A, DBCMD_ZQCL_VAL
201 write32 DBCMD_A, DBCMD_REF_VAL
202 write32 DBCMD_A, DBCMD_REF_VAL
206 write32 DBADJ0_A, DBADJ0_D
207 write32 DBADJ1_A, DBADJ1_D
208 write32 DBADJ2_A, DBADJ2_D
211 write32 DBRFCNF0_A, DBRFCNF0_D
212 write32 DBRFCNF1_A, DBRFCNF1_D
213 write32 DBRFCNF2_A, DBRFCNF2_D
216 write32 DBCALCNF_A, DBCALCNF_D
219 write32 DBRFEN_A, DBRFEN_D
220 write32 DBCMD_A, DBCMD_SRXT_VAL
223 write32 DBACEN_A, DBACEN_D
233 EXPEVT_A: .long 0xff000024
234 EXPEVT_POWER_ON_RESET: .long 0x00000000
236 /*------- Reset -------*/
237 MRSTCR0_A: .long 0xffd50030
238 MRSTCR0_D: .long 0xfe1ffe7f
239 MRSTCR1_A: .long 0xffd50034
240 MRSTCR1_D: .long 0xfff3ffff
242 /*------- DDR3IF -------*/
243 DBCMD_A: .long 0xfe800018
244 DBKIND_A: .long 0xfe800020
245 DBCONF_A: .long 0xfe800024
246 DBTR0_A: .long 0xfe800040
247 DBTR1_A: .long 0xfe800044
248 DBTR2_A: .long 0xfe800048
249 DBTR3_A: .long 0xfe800050
250 DBTR4_A: .long 0xfe800054
251 DBTR5_A: .long 0xfe800058
252 DBTR6_A: .long 0xfe80005c
253 DBTR7_A: .long 0xfe800060
254 DBTR8_A: .long 0xfe800064
255 DBTR9_A: .long 0xfe800068
256 DBTR10_A: .long 0xfe80006c
257 DBTR11_A: .long 0xfe800070
258 DBTR12_A: .long 0xfe800074
259 DBTR13_A: .long 0xfe800078
260 DBTR14_A: .long 0xfe80007c
261 DBTR15_A: .long 0xfe800080
262 DBTR16_A: .long 0xfe800084
263 DBTR17_A: .long 0xfe800088
264 DBTR18_A: .long 0xfe80008c
265 DBTR19_A: .long 0xfe800090
266 DBRNK0_A: .long 0xfe800100
267 DBPDCNT0_A: .long 0xfe800200
268 DBPDCNT1_A: .long 0xfe800204
269 DBPDCNT2_A: .long 0xfe800208
270 DBPDCNT3_A: .long 0xfe80020c
271 DBPDLCK_A: .long 0xfe800280
272 DBPDRGA_A: .long 0xfe800290
273 DBPDRGD_A: .long 0xfe8002a0
274 DBADJ0_A: .long 0xfe8000c0
275 DBADJ1_A: .long 0xfe8000c4
276 DBADJ2_A: .long 0xfe8000c8
277 DBRFCNF0_A: .long 0xfe8000e0
278 DBRFCNF1_A: .long 0xfe8000e4
279 DBRFCNF2_A: .long 0xfe8000e8
280 DBCALCNF_A: .long 0xfe8000f4
281 DBRFEN_A: .long 0xfe800014
282 DBACEN_A: .long 0xfe800010
283 DBWAIT_A: .long 0xfe80001c
285 WAIT_OSC_TIME: .long 6000
286 WAIT_30US: .long 13333
288 DBCMD_RSTL_VAL: .long 0x20000000
289 DBCMD_PDEN_VAL: .long 0x1000d73c
290 DBCMD_WAIT_VAL: .long 0x0000d73c
291 DBCMD_RSTH_VAL: .long 0x2100d73c
292 DBCMD_PDXT_VAL: .long 0x110000c8
293 DBCMD_MRS0_VAL: .long 0x28000930
294 DBCMD_MRS1_VAL: .long 0x29000004
295 DBCMD_MRS2_VAL: .long 0x2a000008
296 DBCMD_MRS3_VAL: .long 0x2b000000
297 DBCMD_ZQCL_VAL: .long 0x03000200
298 DBCMD_REF_VAL: .long 0x0c000000
299 DBCMD_SRXT_VAL: .long 0x19000000
300 DBKIND_D: .long 0x00000007
301 DBCONF_D: .long 0x0f030a01
302 DBTR0_D: .long 0x00000007
303 DBTR1_D: .long 0x00000006
304 DBTR2_D: .long 0x00000000
305 DBTR3_D: .long 0x00000007
306 DBTR4_D: .long 0x00070007
307 DBTR5_D: .long 0x0000001b
308 DBTR6_D: .long 0x00000014
309 DBTR7_D: .long 0x00000005
310 DBTR8_D: .long 0x00000015
311 DBTR9_D: .long 0x00000006
312 DBTR10_D: .long 0x00000008
313 DBTR11_D: .long 0x00000007
314 DBTR12_D: .long 0x0000000e
315 DBTR13_D: .long 0x00000056
316 DBTR14_D: .long 0x00000006
317 DBTR15_D: .long 0x00000004
318 DBTR16_D: .long 0x00150002
319 DBTR17_D: .long 0x000c0017
320 DBTR18_D: .long 0x00000200
321 DBTR19_D: .long 0x00000040
322 DBRNK0_D: .long 0x00000001
323 DBPDCNT0_D: .long 0x00000001
324 DBPDCNT1_D: .long 0x00000001
325 DBPDCNT2_D: .long 0x00000000
326 DBPDCNT3_D: .long 0x00004010
327 DBPDLCK_D: .long 0x0000a55a
328 DBPDRGA_D: .long 0x00000028
329 DBPDRGD_D: .long 0x00017100
331 DBADJ0_D: .long 0x00000000
332 DBADJ1_D: .long 0x00000000
333 DBADJ2_D: .long 0x18061806
334 DBRFCNF0_D: .long 0x000001ff
335 DBRFCNF1_D: .long 0x08001000
336 DBRFCNF2_D: .long 0x00000000
337 DBCALCNF_D: .long 0x0000ffff
338 DBRFEN_D: .long 0x00000001
339 DBACEN_D: .long 0x00000001
343 #if defined(CONFIG_SH_32BIT)
344 /*------- set PMB -------*/
345 write32 PASCR_A, PASCR_29BIT_D
346 write32 MMUCR_A, MMUCR_D
348 /*****************************************************************
349 * ent virt phys v sz c wt
350 * 0 0xa0000000 0x00000000 1 128M 0 1
351 * 1 0xa8000000 0x48000000 1 128M 0 1
352 * 5 0x88000000 0x48000000 1 128M 1 1
354 write32 PMB_ADDR_SPIBOOT_A, PMB_ADDR_SPIBOOT_D
355 write32 PMB_DATA_SPIBOOT_A, PMB_DATA_SPIBOOT_D
356 write32 PMB_ADDR_DDR_C1_A, PMB_ADDR_DDR_C1_D
357 write32 PMB_DATA_DDR_C1_A, PMB_DATA_DDR_C1_D
358 write32 PMB_ADDR_DDR_N1_A, PMB_ADDR_DDR_N1_D
359 write32 PMB_DATA_DDR_N1_A, PMB_DATA_DDR_N1_D
361 write32 PMB_ADDR_ENTRY2, PMB_ADDR_NOT_USE_D
362 write32 PMB_ADDR_ENTRY3, PMB_ADDR_NOT_USE_D
363 write32 PMB_ADDR_ENTRY4, PMB_ADDR_NOT_USE_D
364 write32 PMB_ADDR_ENTRY6, PMB_ADDR_NOT_USE_D
365 write32 PMB_ADDR_ENTRY7, PMB_ADDR_NOT_USE_D
366 write32 PMB_ADDR_ENTRY8, PMB_ADDR_NOT_USE_D
367 write32 PMB_ADDR_ENTRY9, PMB_ADDR_NOT_USE_D
368 write32 PMB_ADDR_ENTRY10, PMB_ADDR_NOT_USE_D
369 write32 PMB_ADDR_ENTRY11, PMB_ADDR_NOT_USE_D
370 write32 PMB_ADDR_ENTRY12, PMB_ADDR_NOT_USE_D
371 write32 PMB_ADDR_ENTRY13, PMB_ADDR_NOT_USE_D
372 write32 PMB_ADDR_ENTRY14, PMB_ADDR_NOT_USE_D
373 write32 PMB_ADDR_ENTRY15, PMB_ADDR_NOT_USE_D
375 write32 PASCR_A, PASCR_INIT
378 #endif /* if defined(CONFIG_SH_32BIT) */
381 /* CPU is running on ILRAM? */
386 mov.l _stack_ilram, r15
387 mov.l _spiboot_main, r0
392 _spiboot_main: .long (spiboot_main - (100b + 4))
393 _stack_ilram: .long 0xe5204000
403 #if defined(CONFIG_SH_32BIT)
404 /*------- set PMB -------*/
405 PMB_ADDR_SPIBOOT_A: .long PMB_ADDR_BASE(0)
406 PMB_ADDR_DDR_N1_A: .long PMB_ADDR_BASE(1)
407 PMB_ADDR_DDR_C1_A: .long PMB_ADDR_BASE(5)
408 PMB_ADDR_ENTRY2: .long PMB_ADDR_BASE(2)
409 PMB_ADDR_ENTRY3: .long PMB_ADDR_BASE(3)
410 PMB_ADDR_ENTRY4: .long PMB_ADDR_BASE(4)
411 PMB_ADDR_ENTRY6: .long PMB_ADDR_BASE(6)
412 PMB_ADDR_ENTRY7: .long PMB_ADDR_BASE(7)
413 PMB_ADDR_ENTRY8: .long PMB_ADDR_BASE(8)
414 PMB_ADDR_ENTRY9: .long PMB_ADDR_BASE(9)
415 PMB_ADDR_ENTRY10: .long PMB_ADDR_BASE(10)
416 PMB_ADDR_ENTRY11: .long PMB_ADDR_BASE(11)
417 PMB_ADDR_ENTRY12: .long PMB_ADDR_BASE(12)
418 PMB_ADDR_ENTRY13: .long PMB_ADDR_BASE(13)
419 PMB_ADDR_ENTRY14: .long PMB_ADDR_BASE(14)
420 PMB_ADDR_ENTRY15: .long PMB_ADDR_BASE(15)
422 PMB_ADDR_SPIBOOT_D: .long mk_pmb_addr_val(0xa0)
423 PMB_ADDR_DDR_C1_D: .long mk_pmb_addr_val(0x88)
424 PMB_ADDR_DDR_N1_D: .long mk_pmb_addr_val(0xa8)
425 PMB_ADDR_NOT_USE_D: .long 0x00000000
427 PMB_DATA_SPIBOOT_A: .long PMB_DATA_BASE(0)
428 PMB_DATA_DDR_N1_A: .long PMB_DATA_BASE(1)
429 PMB_DATA_DDR_C1_A: .long PMB_DATA_BASE(5)
431 /* ppn ub v s1 s0 c wt */
432 PMB_DATA_SPIBOOT_D: .long mk_pmb_data_val(0x00, 0, 1, 1, 0, 0, 1)
433 PMB_DATA_DDR_C1_D: .long mk_pmb_data_val(0x48, 0, 1, 1, 0, 1, 1)
434 PMB_DATA_DDR_N1_D: .long mk_pmb_data_val(0x48, 1, 1, 1, 0, 0, 1)
436 PASCR_A: .long 0xff000070
437 DUMMY_ADDR: .long 0xa0000000
438 PASCR_29BIT_D: .long 0x00000000
439 PASCR_INIT: .long 0x80000080
440 MMUCR_A: .long 0xff000010
441 MMUCR_D: .long 0x00000004 /* clear ITLB */
442 #endif /* CONFIG_SH_32BIT */
445 CCR_D: .long CCR_CACHE_INIT