2 * board/renesas/salvator-x/salvator-x.c
3 * This file is Salvator-X board support.
5 * Copyright (C) 2015-2017 Renesas Electronics Corporation
6 * Copyright (C) 2015 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
8 * SPDX-License-Identifier: GPL-2.0+
15 #include <dm/platform_data/serial_sh.h>
16 #include <asm/processor.h>
17 #include <asm/mach-types.h>
19 #include <linux/errno.h>
20 #include <asm/arch/sys_proto.h>
22 #include <asm/arch/gpio.h>
23 #include <asm/arch/rmobile.h>
24 #include <asm/arch/rcar-mstp.h>
25 #include <asm/arch/sh_sdhi.h>
29 DECLARE_GLOBAL_DATA_PTR;
31 #define CPGWPCR 0xE6150904
32 #define CPGWPR 0xE615090C
34 #define CLK2MHZ(clk) (clk / 1000 / 1000)
37 struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
38 struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
41 writel(0xA5A5A500, &rwdt->rwtcsra);
42 writel(0xA5A5A500, &swdt->swtcsra);
44 writel(0xA5A50000, CPGWPCR);
45 writel(0xFFFFFFFF, CPGWPR);
48 #define GSX_MSTP112 BIT(12) /* 3DG */
49 #define TMU0_MSTP125 BIT(25) /* secure */
50 #define TMU1_MSTP124 BIT(24) /* non-secure */
51 #define SCIF2_MSTP310 BIT(10) /* SCIF2 */
52 #define ETHERAVB_MSTP812 BIT(12)
53 #define DVFS_MSTP926 BIT(26)
54 #define SD0_MSTP314 BIT(14)
55 #define SD1_MSTP313 BIT(13)
56 #define SD2_MSTP312 BIT(12) /* either MMC0 */
57 #define SD3_MSTP311 BIT(11) /* either MMC1 */
59 #define SD0CKCR 0xE6150074
60 #define SD1CKCR 0xE6150078
61 #define SD2CKCR 0xE6150268
62 #define SD3CKCR 0xE615026C
64 int board_early_init_f(void)
66 /* TMU0,1 */ /* which use ? */
67 mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125 | TMU1_MSTP124);
69 mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SCIF2_MSTP310);
71 mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHERAVB_MSTP812);
73 mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SD1_MSTP313 | SD2_MSTP312);
75 mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SD0_MSTP314 | SD3_MSTP311);
82 #if defined(CONFIG_SYS_I2C) && defined(CONFIG_SYS_I2C_SH)
84 mstp_clrbits_le32(MSTPSR9, SMSTPCR9, DVFS_MSTP926);
90 /* R/- 32 Power status register 2(3DG) */
91 #define SYSC_PWRSR2 0xE6180100
92 /* -/W 32 Power resume control register 2 (3DG) */
93 #define SYSC_PWRONCR2 0xE618010C
97 /* adress of boot parameters */
98 gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000;
100 /* Init PFC controller */
101 r8a7795_pinmux_init();
103 /* GSX: force power and clock supply */
104 writel(0x0000001F, SYSC_PWRONCR2);
105 while (readl(SYSC_PWRSR2) != 0x000003E0)
108 mstp_clrbits_le32(MSTPSR1, SMSTPCR1, GSX_MSTP112);
111 /* EtherAVB Enable */
113 gpio_request(GPIO_GFN_AVB_AVTP_CAPTURE_A, NULL);
114 gpio_request(GPIO_GFN_AVB_AVTP_MATCH_A, NULL);
115 gpio_request(GPIO_GFN_AVB_LINK, NULL);
116 gpio_request(GPIO_GFN_AVB_PHY_INT, NULL);
117 gpio_request(GPIO_GFN_AVB_MAGIC, NULL);
118 gpio_request(GPIO_GFN_AVB_MDC, NULL);
121 gpio_request(GPIO_IFN_AVB_MDC, NULL);
122 gpio_request(GPIO_IFN_AVB_MAGIC, NULL);
123 gpio_request(GPIO_IFN_AVB_PHY_INT, NULL);
124 gpio_request(GPIO_IFN_AVB_LINK, NULL);
125 gpio_request(GPIO_IFN_AVB_AVTP_MATCH_A, NULL);
126 gpio_request(GPIO_IFN_AVB_AVTP_CAPTURE_A, NULL);
128 gpio_request(GPIO_FN_AVB_AVTP_PPS, NULL);
130 gpio_request(GPIO_FN_AVB_AVTP_MATCH_B, NULL);
132 gpio_request(GPIO_FN_AVB_AVTP_CAPTURE_B, NULL);
135 gpio_request(GPIO_GP_2_10, NULL);
136 gpio_direction_output(GPIO_GP_2_10, 0);
138 gpio_set_value(GPIO_GP_2_10, 1);
145 static struct eth_pdata salvator_x_ravb_platdata = {
146 .iobase = 0xE6800000,
151 U_BOOT_DEVICE(salvator_x_ravb) = {
153 .platdata = &salvator_x_ravb_platdata,
156 #ifdef CONFIG_SH_SDHI
157 int board_mmc_init(bd_t *bis)
162 gpio_request(GPIO_GFN_SD0_DAT0, NULL);
163 gpio_request(GPIO_GFN_SD0_DAT1, NULL);
164 gpio_request(GPIO_GFN_SD0_DAT2, NULL);
165 gpio_request(GPIO_GFN_SD0_DAT3, NULL);
166 gpio_request(GPIO_GFN_SD0_CLK, NULL);
167 gpio_request(GPIO_GFN_SD0_CMD, NULL);
168 gpio_request(GPIO_GFN_SD0_CD, NULL);
169 gpio_request(GPIO_GFN_SD0_WP, NULL);
171 gpio_request(GPIO_GP_5_2, NULL);
172 gpio_request(GPIO_GP_5_1, NULL);
173 gpio_direction_output(GPIO_GP_5_2, 1); /* power on */
174 gpio_direction_output(GPIO_GP_5_1, 1); /* 1: 3.3V, 0: 1.8V */
176 ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI0_BASE, 0,
177 SH_SDHI_QUIRK_64BIT_BUF);
181 /* SDHI1/SDHI2 eMMC */
182 gpio_request(GPIO_GFN_SD1_DAT0, NULL);
183 gpio_request(GPIO_GFN_SD1_DAT1, NULL);
184 gpio_request(GPIO_GFN_SD1_DAT2, NULL);
185 gpio_request(GPIO_GFN_SD1_DAT3, NULL);
186 gpio_request(GPIO_GFN_SD2_DAT0, NULL);
187 gpio_request(GPIO_GFN_SD2_DAT1, NULL);
188 gpio_request(GPIO_GFN_SD2_DAT2, NULL);
189 gpio_request(GPIO_GFN_SD2_DAT3, NULL);
190 gpio_request(GPIO_GFN_SD2_CLK, NULL);
191 gpio_request(GPIO_GFN_SD2_CMD, NULL);
192 gpio_request(GPIO_GP_5_3, NULL);
193 gpio_request(GPIO_GP_5_9, NULL);
194 gpio_direction_output(GPIO_GP_5_3, 0); /* 1: 3.3V, 0: 1.8V */
195 gpio_direction_output(GPIO_GP_5_9, 0); /* 1: 3.3V, 0: 1.8V */
197 ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI2_BASE, 1,
198 SH_SDHI_QUIRK_64BIT_BUF);
203 gpio_request(GPIO_GFN_SD3_DAT0, NULL); /* GP_4_9 */
204 gpio_request(GPIO_GFN_SD3_DAT1, NULL); /* GP_4_10 */
205 gpio_request(GPIO_GFN_SD3_DAT2, NULL); /* GP_4_11 */
206 gpio_request(GPIO_GFN_SD3_DAT3, NULL); /* GP_4_12 */
207 gpio_request(GPIO_GFN_SD3_CLK, NULL); /* GP_4_7 */
208 gpio_request(GPIO_GFN_SD3_CMD, NULL); /* GP_4_8 */
210 gpio_request(GPIO_FN_SD3_CD, NULL);
211 gpio_request(GPIO_FN_SD3_WP, NULL);
213 gpio_request(GPIO_GP_3_15, NULL);
214 gpio_request(GPIO_GP_3_14, NULL);
215 gpio_direction_output(GPIO_GP_3_15, 1); /* power on */
216 gpio_direction_output(GPIO_GP_3_14, 1); /* 1: 3.3V, 0: 1.8V */
218 ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI3_BASE, 2,
219 SH_SDHI_QUIRK_64BIT_BUF);
226 gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
231 const struct rmobile_sysinfo sysinfo = {
232 CONFIG_RCAR_BOARD_STRING
235 #define RST_BASE 0xE6160000
236 #define RST_CA57RESCNT (RST_BASE + 0x40)
237 #define RST_CA53RESCNT (RST_BASE + 0x44)
238 #define RST_RSTOUTCR (RST_BASE + 0x58)
239 #define RST_CODE 0xA5A5000F
241 void reset_cpu(ulong addr)
243 #if defined(CONFIG_SYS_I2C) && defined(CONFIG_SYS_I2C_SH)
244 i2c_reg_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x20, 0x80);
247 writel(RST_CODE, RST_CA57RESCNT);
251 static const struct sh_serial_platdata serial_platdata = {
254 .clk = CONFIG_SH_SCIF_CLK_FREQ,
258 U_BOOT_DEVICE(salvator_x_scif2) = {
260 .platdata = &serial_platdata,