board/renesas/rsk7203/lowlevel_init.S

   1 /*
   2  * Copyright (C) 2008 Nobuhiro Iwamatsu
   3  * Copyright (C) 2008 Renesas Solutions Corp.
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License as
   7  * published by the Free Software Foundation; either version 2 of
   8  * the License, or (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  18  * MA 02111-1307 USA
  19  */
  20 #include <config.h>
  21 #include <version.h>
  22
  23 #include <asm/processor.h>
  24 #include <asm/macro.h>
  25
  26         .global lowlevel_init
  27
  28         .text
  29         .align  2
  30
  31 lowlevel_init:
  32         /* Cache setting */
  33         write32 CCR1_A ,CCR1_D
  34
  35         /* ConfigurePortPins */
  36         write16 PECRL3_A, PECRL3_D
  37
  38         write16 PCCRL4_A, PCCRL4_D0
  39
  40         write16 PECRL4_A, PECRL4_D0
  41
  42         write16 PEIORL_A, PEIORL_D0
  43
  44         write16 PCIORL_A, PCIORL_D
  45
  46         write16 PFCRH2_A, PFCRH2_D
  47
  48         write16 PFCRH3_A, PFCRH3_D
  49
  50         write16 PFCRH1_A, PFCRH1_D
  51
  52         write16 PFIORH_A, PFIORH_D
  53
  54         write16 PECRL1_A, PECRL1_D0
  55
  56         write16 PEIORL_A, PEIORL_D1
  57
  58         /* Configure Operating Frequency */
  59         write16 WTCSR_A, WTCSR_D0
  60
  61         write16 WTCSR_A, WTCSR_D1
  62
  63         write16 WTCNT_A, WTCNT_D
  64
  65         /* Set clock mode*/
  66         write16 FRQCR_A, FRQCR_D
  67
  68         /* Configure Bus And Memory */
  69 init_bsc_cs0:
  70         write16 PCCRL4_A, PCCRL4_D1
  71
  72         write16 PECRL1_A, PECRL1_D1
  73
  74         write32 CMNCR_A, CMNCR_D
  75
  76         write32 SC0BCR_A, SC0BCR_D
  77
  78         write32 CS0WCR_A, CS0WCR_D
  79
  80 init_bsc_cs1:
  81         write16 PECRL4_A, PECRL4_D1
  82
  83         write32 CS1WCR_A, CS1WCR_D
  84
  85 init_sdram:
  86         write16 PCCRL2_A, PCCRL2_D
  87
  88         write16 PCCRL4_A, PCCRL4_D2
  89
  90         write16 PCCRL1_A, PCCRL1_D
  91
  92         write16 PCCRL3_A, PCCRL3_D
  93
  94         write32 CS3BCR_A, CS3BCR_D
  95
  96         write32 CS3WCR_A, CS3WCR_D
  97
  98         write32 SDCR_A, SDCR_D
  99
 100         write32 RTCOR_A, RTCOR_D
 101
 102         write32 RTCSR_A, RTCSR_D
 103
 104         /* wait 200us */
 105         mov.l   REPEAT_D, r3
 106         mov     #0, r2
 107 repeat0:
 108         add     #1, r2
 109         cmp/hs  r3, r2
 110         bf      repeat0
 111         nop
 112
 113         mov.l   SDRAM_MODE, r1
 114         mov     #0, r0
 115         mov.l   r0, @r1
 116
 117         nop
 118         rts
 119
 120         .align 4
 121
 122 CCR1_A:         .long CCR1
 123 CCR1_D:         .long 0x0000090B
 124 PCCRL4_A:       .long 0xFFFE3910
 125 PCCRL4_D0:      .long 0x00000000
 126 PECRL4_A:       .long 0xFFFE3A10
 127 PECRL4_D0:      .long 0x00000000
 128 PECRL3_A:       .long 0xFFFE3A12
 129 PECRL3_D:       .long 0x00000000
 130 PEIORL_A:       .long 0xFFFE3A06
 131 PEIORL_D0:      .long 0x00001C00
 132 PEIORL_D1:      .long 0x00001C02
 133 PCIORL_A:       .long 0xFFFE3906
 134 PCIORL_D:       .long 0x00004000
 135 PFCRH2_A:       .long 0xFFFE3A8C
 136 PFCRH2_D:       .long 0x00000000
 137 PFCRH3_A:       .long 0xFFFE3A8A
 138 PFCRH3_D:       .long 0x00000000
 139 PFCRH1_A:       .long 0xFFFE3A8E
 140 PFCRH1_D:       .long 0x00000000
 141 PFIORH_A:       .long 0xFFFE3A84
 142 PFIORH_D:       .long 0x00000729
 143 PECRL1_A:       .long 0xFFFE3A16
 144 PECRL1_D0:      .long 0x00000033
 145
 146
 147 WTCSR_A:        .long 0xFFFE0000
 148 WTCSR_D0:       .long 0x0000A518
 149 WTCSR_D1:       .long 0x0000A51D
 150 WTCNT_A:        .long 0xFFFE0002
 151 WTCNT_D:        .long 0x00005A84
 152 FRQCR_A:        .long 0xFFFE0010
 153 FRQCR_D:        .long 0x00000104
 154
 155 PCCRL4_D1:      .long 0x00000010
 156 PECRL1_D1:      .long 0x00000133
 157
 158 CMNCR_A:        .long 0xFFFC0000
 159 CMNCR_D:        .long 0x00001810
 160 SC0BCR_A:       .long 0xFFFC0004
 161 SC0BCR_D:       .long 0x10000400
 162 CS0WCR_A:       .long 0xFFFC0028
 163 CS0WCR_D:       .long 0x00000B41
 164 PECRL4_D1:      .long 0x00000100
 165 CS1WCR_A:       .long 0xFFFC002C
 166 CS1WCR_D:       .long 0x00000B01
 167 PCCRL4_D2:      .long 0x00000011
 168 PCCRL3_A:       .long 0xFFFE3912
 169 PCCRL3_D:       .long 0x00000011
 170 PCCRL2_A:       .long 0xFFFE3914
 171 PCCRL2_D:       .long 0x00001111
 172 PCCRL1_A:       .long 0xFFFE3916
 173 PCCRL1_D:       .long 0x00001010
 174 PDCRL4_A:       .long 0xFFFE3990
 175 PDCRL4_D:       .long 0x00000011
 176 PDCRL3_A:       .long 0xFFFE3992
 177 PDCRL3_D:       .long 0x00000011
 178 PDCRL2_A:       .long 0xFFFE3994
 179 PDCRL2_D:       .long 0x00001111
 180 PDCRL1_A:       .long 0xFFFE3996
 181 PDCRL1_D:       .long 0x00001000
 182 CS3BCR_A:       .long 0xFFFC0010
 183 CS3BCR_D:       .long 0x00004400
 184 CS3WCR_A:       .long 0xFFFC0034
 185 CS3WCR_D:       .long 0x00002892
 186 SDCR_A:         .long 0xFFFC004C
 187 SDCR_D:         .long 0x00000809
 188 RTCOR_A:        .long 0xFFFC0058
 189 RTCOR_D:        .long 0xA55A0041
 190 RTCSR_A:        .long 0xFFFC0050
 191 RTCSR_D:        .long 0xa55a0010
 192
 193 STBCR3_A:       .long 0xFFFE0408
 194 STBCR3_D:       .long 0x00000000
 195 STBCR4_A:       .long 0xFFFE040C
 196 STBCR4_D:       .long 0x00000008
 197 STBCR5_A:       .long 0xFFFE0410
 198 STBCR5_D:       .long 0x00000000
 199 STBCR6_A:       .long 0xFFFE0414
 200 STBCR6_D:       .long 0x00000002
 201 SDRAM_MODE:     .long 0xFFFC5040
 202 REPEAT_D:       .long 0x00009C40