2 * Copyright (C) 2007,2008 Nobuhiro Iwamatsu
4 * u-boot/board/r7780mp/lowlevel_init.S
6 * SPDX-License-Identifier: GPL-2.0+
11 #include <asm/processor.h>
12 #include <asm/macro.h>
15 * Board specific low level init code, called _very_ early in the
16 * startup sequence. Relocation to SDRAM has not happened yet, no
17 * stack is available, bss section has not been initialised, etc.
19 * (Note: As no stack is available, no subroutines can be called...).
29 write32 CCR_A, CCR_D /* Address of Cache Control Register */
30 /* Instruction Cache Invalidate */
32 write32 FRQCR_A, FRQCR_D /* Frequency control register */
34 /* pin_multi_setting */
35 write32 BBG_PMMR_A, BBG_PMMR_D_PMSR1
37 write32 BBG_PMSR1_A, BBG_PMSR1_D
39 write32 BBG_PMMR_A, BBG_PMMR_D_PMSR2
41 write32 BBG_PMSR2_A, BBG_PMSR2_D
43 write32 BBG_PMMR_A, BBG_PMMR_D_PMSR3
45 write32 BBG_PMSR3_A, BBG_PMSR3_D
47 write32 BBG_PMMR_A, BBG_PMMR_D_PMSR4
49 write32 BBG_PMSR4_A, BBG_PMSR4_D
51 write32 BBG_PMMR_A, BBG_PMMR_D_PMSRG
53 write32 BBG_PMSRG_A, BBG_PMSRG_D
56 write32 FRQCR_A, FRQCR_D
58 write32 DLLCSR_A, DLLCSR_D
81 write32 MMSELR_A, MMSELR_D
85 write32 CS0BCR_A, CS0BCR_D
87 write32 CS1BCR_A, CS1BCR_D
89 write32 CS2BCR_A, CS2BCR_D
91 write32 CS4BCR_A, CS4BCR_D
93 write32 CS5BCR_A, CS5BCR_D
95 write32 CS6BCR_A, CS6BCR_D
97 write32 CS0WCR_A, CS0WCR_D
99 write32 CS1WCR_A, CS1WCR_D
101 write32 CS2WCR_A, CS2WCR_D
103 write32 CS4WCR_A, CS4WCR_D
105 write32 CS5WCR_A, CS5WCR_D
107 write32 CS6WCR_A, CS6WCR_D
109 write32 CS5PCR_A, CS5PCR_D
111 write32 CS6PCR_A, CS6PCR_D
254 RWTCSR_D_1: .word 0xA507
255 RWTCSR_D_2: .word 0xA507
256 RWTCNT_D: .word 0x5A00
259 BBG_PMMR_A: .long 0xFF800010
260 BBG_PMSR1_A: .long 0xFF800014
261 BBG_PMSR2_A: .long 0xFF800018
262 BBG_PMSR3_A: .long 0xFF80001C
263 BBG_PMSR4_A: .long 0xFF800020
264 BBG_PMSRG_A: .long 0xFF800024
266 BBG_PMMR_D_PMSR1: .long 0xffffbffd
267 BBG_PMSR1_D: .long 0x00004002
268 BBG_PMMR_D_PMSR2: .long 0xfc21a7ff
269 BBG_PMSR2_D: .long 0x03de5800
270 BBG_PMMR_D_PMSR3: .long 0xfffffff8
271 BBG_PMSR3_D: .long 0x00000007
272 BBG_PMMR_D_PMSR4: .long 0xdffdfff9
273 BBG_PMSR4_D: .long 0x20020006
274 BBG_PMMR_D_PMSRG: .long 0xffffffff
275 BBG_PMSRG_D: .long 0x00000000
278 DLLCSR_A: .long 0xffc40010
279 FRQCR_D: .long 0x40233035
280 DLLCSR_D: .long 0x00000000
292 EMRS_A: .long 0xFEC02000
293 MRS1_A: .long 0xFEC00B08
294 MRS2_A: .long 0xFEC00308
296 MIM_U_D: .long 0x00004000
297 MIM_L_D0: .long 0x03e80009
298 MIM_L_D1: .long 0x03e80209
305 STR_L_D: .long 0x000f0000
306 SDR_L_D: .long 0x00000400
311 /* Cache Controller */
314 RWTCNT_A: .long WTCNT
316 CCR_D: .long 0x0000090b
317 CCR_D_2: .long 0x00000103
318 MMUCR_D: .long 0x00000004
319 MSTPCR0_D: .long 0x00001001
320 MSTPCR2_D: .long 0xffffffff
322 /* local Bus State Controller */
323 MMSELR_A: .long MMSELR
325 CS0BCR_A: .long CS0BCR
326 CS1BCR_A: .long CS1BCR
327 CS2BCR_A: .long CS2BCR
328 CS4BCR_A: .long CS4BCR
329 CS5BCR_A: .long CS5BCR
330 CS6BCR_A: .long CS6BCR
331 CS0WCR_A: .long CS0WCR
332 CS1WCR_A: .long CS1WCR
333 CS2WCR_A: .long CS2WCR
334 CS4WCR_A: .long CS4WCR
335 CS5WCR_A: .long CS5WCR
336 CS6WCR_A: .long CS6WCR
337 CS5PCR_A: .long CS5PCR
338 CS6PCR_A: .long CS6PCR
340 MMSELR_D: .long 0xA5A50003
341 BCR_D: .long 0x00000000
342 CS0BCR_D: .long 0x77777770
343 CS1BCR_D: .long 0x77777670
344 CS2BCR_D: .long 0x77777770
345 CS4BCR_D: .long 0x77777770
346 CS5BCR_D: .long 0x77777670
347 CS6BCR_D: .long 0x77777770
348 CS0WCR_D: .long 0x00020006
349 CS1WCR_D: .long 0x00232304
350 CS2WCR_D: .long 0x7777770F
351 CS4WCR_D: .long 0x7777770F
352 CS5WCR_D: .long 0x00101006
353 CS6WCR_D: .long 0x77777703
354 CS5PCR_D: .long 0x77000000
355 CS6PCR_D: .long 0x77000000
357 REPEAT0_R3: .long 0x00002000
358 REPEAT0_R1: .long 0x0000200