2 * Copyright (C) 2007,2008 Nobuhiro Iwamatsu
4 * u-boot/board/r7780mp/lowlevel_init.S
6 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/processor.h>
11 #include <asm/macro.h>
14 * Board specific low level init code, called _very_ early in the
15 * startup sequence. Relocation to SDRAM has not happened yet, no
16 * stack is available, bss section has not been initialised, etc.
18 * (Note: As no stack is available, no subroutines can be called...).
28 write32 CCR_A, CCR_D /* Address of Cache Control Register */
29 /* Instruction Cache Invalidate */
31 write32 FRQCR_A, FRQCR_D /* Frequency control register */
33 /* pin_multi_setting */
34 write32 BBG_PMMR_A, BBG_PMMR_D_PMSR1
36 write32 BBG_PMSR1_A, BBG_PMSR1_D
38 write32 BBG_PMMR_A, BBG_PMMR_D_PMSR2
40 write32 BBG_PMSR2_A, BBG_PMSR2_D
42 write32 BBG_PMMR_A, BBG_PMMR_D_PMSR3
44 write32 BBG_PMSR3_A, BBG_PMSR3_D
46 write32 BBG_PMMR_A, BBG_PMMR_D_PMSR4
48 write32 BBG_PMSR4_A, BBG_PMSR4_D
50 write32 BBG_PMMR_A, BBG_PMMR_D_PMSRG
52 write32 BBG_PMSRG_A, BBG_PMSRG_D
55 write32 FRQCR_A, FRQCR_D
57 write32 DLLCSR_A, DLLCSR_D
80 write32 MMSELR_A, MMSELR_D
84 write32 CS0BCR_A, CS0BCR_D
86 write32 CS1BCR_A, CS1BCR_D
88 write32 CS2BCR_A, CS2BCR_D
90 write32 CS4BCR_A, CS4BCR_D
92 write32 CS5BCR_A, CS5BCR_D
94 write32 CS6BCR_A, CS6BCR_D
96 write32 CS0WCR_A, CS0WCR_D
98 write32 CS1WCR_A, CS1WCR_D
100 write32 CS2WCR_A, CS2WCR_D
102 write32 CS4WCR_A, CS4WCR_D
104 write32 CS5WCR_A, CS5WCR_D
106 write32 CS6WCR_A, CS6WCR_D
108 write32 CS5PCR_A, CS5PCR_D
110 write32 CS6PCR_A, CS6PCR_D
253 RWTCSR_D_1: .word 0xA507
254 RWTCSR_D_2: .word 0xA507
255 RWTCNT_D: .word 0x5A00
258 BBG_PMMR_A: .long 0xFF800010
259 BBG_PMSR1_A: .long 0xFF800014
260 BBG_PMSR2_A: .long 0xFF800018
261 BBG_PMSR3_A: .long 0xFF80001C
262 BBG_PMSR4_A: .long 0xFF800020
263 BBG_PMSRG_A: .long 0xFF800024
265 BBG_PMMR_D_PMSR1: .long 0xffffbffd
266 BBG_PMSR1_D: .long 0x00004002
267 BBG_PMMR_D_PMSR2: .long 0xfc21a7ff
268 BBG_PMSR2_D: .long 0x03de5800
269 BBG_PMMR_D_PMSR3: .long 0xfffffff8
270 BBG_PMSR3_D: .long 0x00000007
271 BBG_PMMR_D_PMSR4: .long 0xdffdfff9
272 BBG_PMSR4_D: .long 0x20020006
273 BBG_PMMR_D_PMSRG: .long 0xffffffff
274 BBG_PMSRG_D: .long 0x00000000
277 DLLCSR_A: .long 0xffc40010
278 FRQCR_D: .long 0x40233035
279 DLLCSR_D: .long 0x00000000
291 EMRS_A: .long 0xFEC02000
292 MRS1_A: .long 0xFEC00B08
293 MRS2_A: .long 0xFEC00308
295 MIM_U_D: .long 0x00004000
296 MIM_L_D0: .long 0x03e80009
297 MIM_L_D1: .long 0x03e80209
304 STR_L_D: .long 0x000f0000
305 SDR_L_D: .long 0x00000400
310 /* Cache Controller */
313 RWTCNT_A: .long WTCNT
315 CCR_D: .long 0x0000090b
316 CCR_D_2: .long 0x00000103
317 MMUCR_D: .long 0x00000004
318 MSTPCR0_D: .long 0x00001001
319 MSTPCR2_D: .long 0xffffffff
321 /* local Bus State Controller */
322 MMSELR_A: .long MMSELR
324 CS0BCR_A: .long CS0BCR
325 CS1BCR_A: .long CS1BCR
326 CS2BCR_A: .long CS2BCR
327 CS4BCR_A: .long CS4BCR
328 CS5BCR_A: .long CS5BCR
329 CS6BCR_A: .long CS6BCR
330 CS0WCR_A: .long CS0WCR
331 CS1WCR_A: .long CS1WCR
332 CS2WCR_A: .long CS2WCR
333 CS4WCR_A: .long CS4WCR
334 CS5WCR_A: .long CS5WCR
335 CS6WCR_A: .long CS6WCR
336 CS5PCR_A: .long CS5PCR
337 CS6PCR_A: .long CS6PCR
339 MMSELR_D: .long 0xA5A50003
340 BCR_D: .long 0x00000000
341 CS0BCR_D: .long 0x77777770
342 CS1BCR_D: .long 0x77777670
343 CS2BCR_D: .long 0x77777770
344 CS4BCR_D: .long 0x77777770
345 CS5BCR_D: .long 0x77777670
346 CS6BCR_D: .long 0x77777770
347 CS0WCR_D: .long 0x00020006
348 CS1WCR_D: .long 0x00232304
349 CS2WCR_D: .long 0x7777770F
350 CS4WCR_D: .long 0x7777770F
351 CS5WCR_D: .long 0x00101006
352 CS6WCR_D: .long 0x77777703
353 CS5PCR_D: .long 0x77000000
354 CS6PCR_D: .long 0x77000000
356 REPEAT0_R3: .long 0x00002000
357 REPEAT0_R1: .long 0x0000200