board/renesas/r2dplus/lowlevel_init.S

   1 /*
   2  * modified from SH-IPL+g (init-r0p751rlc0011rl.S)
   3  * Initial Register Data for R0P751RLC0011RL (SH7751R 240MHz/120MHz/60MHz)
   4  * Coyright (c) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
   5 */
   6
   7 #include <config.h>
   8
   9 #include <asm/processor.h>
  10 #include <asm/macro.h>
  11
  12         .global lowlevel_init
  13         .text
  14         .align  2
  15
  16 lowlevel_init:
  17
  18         write32 CCR_A, CCR_D_D
  19
  20         write32 MMUCR_A, MMUCR_D
  21
  22         write32 BCR1_A, BCR1_D
  23
  24         write16 BCR2_A, BCR2_D
  25
  26         write16 BCR3_A, BCR3_D
  27
  28         write32 BCR4_A, BCR4_D
  29
  30         write32 WCR1_A, WCR1_D
  31
  32         write32 WCR2_A, WCR2_D
  33
  34         write32 WCR3_A, WCR3_D
  35
  36         write16 PCR_A, PCR_D
  37
  38         write16 LED_A, LED_D
  39
  40         write32 MCR_A, MCR_D1
  41
  42         write16 RTCNT_A, RTCNT_D
  43
  44         write16 RTCOR_A, RTCOR_D
  45
  46         write16 RFCR_A, RFCR_D
  47
  48         write16 RTCSR_A, RTCSR_D
  49
  50         write8  SDMR3_A, SDMR3_D0
  51
  52         /* Wait DRAM refresh 30 times */
  53         mov.l   RFCR_A, r1
  54         mov     #30, r3
  55 1:
  56         mov.w   @r1, r0
  57         extu.w  r0, r2
  58         cmp/hi  r3, r2
  59         bf      1b
  60
  61         write32 MCR_A, MCR_D2
  62
  63         write8  SDMR3_A, SDMR3_D1
  64
  65         write32 IRLMASK_A, IRLMASK_D
  66
  67         write32 CCR_A, CCR_D_E
  68
  69         rts
  70         nop
  71
  72         .align  2
  73 CCR_A:          .long   CCR             /* Cache Control Register */
  74 CCR_D_D:        .long   0x0808          /* Flush the cache, disable */
  75 CCR_D_E:        .long   0x8000090B
  76
  77 FRQCR_A:        .long   FRQCR           /* FRQCR Address */
  78 FRQCR_D:        .long   0x00000e0a      /* 03/07/15 modify */
  79 BCR1_A:         .long   BCR1            /* BCR1 Address */
  80 BCR1_D:         .long   0x00180008
  81 BCR2_A:         .long   BCR2            /* BCR2 Address */
  82 BCR2_D:         .long   0xabe8
  83 BCR3_A:         .long   BCR3            /* BCR3 Address */
  84 BCR3_D:         .long   0x0000
  85 BCR4_A:         .long   BCR4            /* BCR4 Address */
  86 BCR4_D:         .long   0x00000010
  87 WCR1_A:         .long   WCR1            /* WCR1 Address */
  88 WCR1_D:         .long   0x33343333
  89 WCR2_A:         .long   WCR2            /* WCR2 Address */
  90 WCR2_D:         .long   0xcff86fbf
  91 WCR3_A:         .long   WCR3            /* WCR3 Address */
  92 WCR3_D:         .long   0x07777707
  93 LED_A:          .long   0x04000036      /* LED Address */
  94 LED_D:          .long   0xFF            /* LED Data */
  95 RTCNT_A:        .long   RTCNT           /* RTCNT Address */
  96 RTCNT_D:        .word   0xA500          /* RTCNT Write Code A5h Data 00h */
  97 .align 2
  98 RTCOR_A:        .long   RTCOR           /* RTCOR Address */
  99 RTCOR_D:        .word   0xA534          /* RTCOR Write Code */
 100 .align 2
 101 RTCSR_A:        .long   RTCSR           /* RTCSR Address */
 102 RTCSR_D:        .word   0xA510          /* RTCSR Write Code */
 103 .align 2
 104 SDMR3_A:        .long   0xFF9400CC      /* SDMR3 Address */
 105 SDMR3_D0:       .long   0x55
 106 SDMR3_D1:       .long   0x00
 107 MCR_A:          .long   MCR             /* MCR Address */
 108 MCR_D1:         .long   0x081901F4      /* MRSET:'0' */
 109 MCR_D2:         .long   0x481901F4      /* MRSET:'1' */
 110 RFCR_A:         .long   RFCR            /* RFCR Address */
 111 RFCR_D:         .long   0xA400          /* RFCR Write Code A4h Data 00h */
 112 PCR_A:          .long   PCR             /* PCR Address */
 113 PCR_D:          .long   0x0000
 114 MMUCR_A:        .long   MMUCR           /* MMUCCR Address */
 115 MMUCR_D:        .long   0x00000000      /* MMUCCR Data */
 116 IRLMASK_A:      .long   0xA4000000      /* IRLMASK Address */
 117 IRLMASK_D:      .long   0x00000000      /* IRLMASK Data */