board/renesas/porter/porter_spl.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * board/renesas/porter/porter_spl.c
   4  *
   5  * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
   6  */
   7
   8 #include <common.h>
   9 #include <cpu_func.h>
  10 #include <malloc.h>
  11 #include <dm/platform_data/serial_sh.h>
  12 #include <asm/processor.h>
  13 #include <asm/mach-types.h>
  14 #include <asm/io.h>
  15 #include <linux/errno.h>
  16 #include <asm/arch/sys_proto.h>
  17 #include <asm/gpio.h>
  18 #include <asm/arch/rmobile.h>
  19 #include <asm/arch/rcar-mstp.h>
  20
  21 #include <spl.h>
  22
  23 #define TMU0_MSTP125    BIT(25)
  24 #define SCIF0_MSTP721   BIT(21)
  25 #define QSPI_MSTP917    BIT(17)
  26
  27 #define SD2CKCR         0xE615026C
  28 #define SD_97500KHZ     0x7
  29
  30 struct reg_config {
  31         u16     off;
  32         u32     val;
  33 };
  34
  35 static void dbsc_wait(u16 reg)
  36 {
  37         static const u32 dbsc3_0_base = DBSC3_0_BASE;
  38         static const u32 dbsc3_1_base = DBSC3_0_BASE + 0x10000;
  39
  40         while (!(readl(dbsc3_0_base + reg) & BIT(0)))
  41                 ;
  42
  43         while (!(readl(dbsc3_1_base + reg) & BIT(0)))
  44                 ;
  45 }
  46
  47 static void spl_init_sys(void)
  48 {
  49         u32 r0 = 0;
  50
  51         writel(0xa5a5a500, 0xe6020004);
  52         writel(0xa5a5a500, 0xe6030004);
  53
  54         asm volatile(
  55                 /* ICIALLU - Invalidate I$ to PoU */
  56                 "mcr    15, 0, %0, cr7, cr5, 0  \n"
  57                 /* BPIALL - Invalidate branch predictors */
  58                 "mcr    15, 0, %0, cr7, cr5, 6  \n"
  59                 /* Set SCTLR[IZ] */
  60                 "mrc    15, 0, %0, cr1, cr0, 0  \n"
  61                 "orr    %0, #0x1800             \n"
  62                 "mcr    15, 0, %0, cr1, cr0, 0  \n"
  63                 "isb    sy                      \n"
  64                 :"=r"(r0));
  65 }
  66
  67 static void spl_init_pfc(void)
  68 {
  69         static const struct reg_config pfc_with_unlock[] = {
  70                 { 0x0090, 0x60000000 },
  71                 { 0x0094, 0x60000000 },
  72                 { 0x0098, 0x00800200 },
  73                 { 0x009c, 0x00000000 },
  74                 { 0x0020, 0x00000000 },
  75                 { 0x0024, 0x00000000 },
  76                 { 0x0028, 0x000244c8 },
  77                 { 0x002c, 0x00000000 },
  78                 { 0x0030, 0x00002400 },
  79                 { 0x0034, 0x01520000 },
  80                 { 0x0038, 0x00724003 },
  81                 { 0x003c, 0x00000000 },
  82                 { 0x0040, 0x00000000 },
  83                 { 0x0044, 0x00000000 },
  84                 { 0x0048, 0x00000000 },
  85                 { 0x004c, 0x00000000 },
  86                 { 0x0050, 0x00000000 },
  87                 { 0x0054, 0x00000000 },
  88                 { 0x0058, 0x00000000 },
  89                 { 0x005c, 0x00000000 },
  90                 { 0x0160, 0x00000000 },
  91                 { 0x0004, 0xffffffff },
  92                 { 0x0008, 0x00ec3fff },
  93                 { 0x000c, 0x3bc001e7 },
  94                 { 0x0010, 0x5bffffff },
  95                 { 0x0014, 0x1ffffffb },
  96                 { 0x0018, 0x01bffff0 },
  97                 { 0x001c, 0xcf7fffff },
  98                 { 0x0074, 0x0381fc00 },
  99         };
 100
 101         static const struct reg_config pfc_without_unlock[] = {
 102                 { 0x0100, 0xffffffdf },
 103                 { 0x0104, 0xc883c3ff },
 104                 { 0x0108, 0x1201f3c9 },
 105                 { 0x010c, 0x00000000 },
 106                 { 0x0110, 0xffffeb04 },
 107                 { 0x0114, 0xc003ffff },
 108                 { 0x0118, 0x0800000f },
 109                 { 0x011c, 0x00187ff0 },
 110         };
 111
 112         static const u32 pfc_base = 0xe6060000;
 113
 114         unsigned int i;
 115
 116         for (i = 0; i < ARRAY_SIZE(pfc_with_unlock); i++) {
 117                 writel(~pfc_with_unlock[i].val, pfc_base);
 118                 writel(pfc_with_unlock[i].val,
 119                        pfc_base | pfc_with_unlock[i].off);
 120         }
 121
 122         for (i = 0; i < ARRAY_SIZE(pfc_without_unlock); i++)
 123                 writel(pfc_without_unlock[i].val,
 124                        pfc_base | pfc_without_unlock[i].off);
 125 }
 126
 127 static void spl_init_gpio(void)
 128 {
 129         static const u16 gpio_offs[] = {
 130                 0x1000, 0x2000, 0x3000, 0x4000, 0x5000, 0x5400, 0x5800
 131         };
 132
 133         static const struct reg_config gpio_set[] = {
 134                 { 0x2000, 0x04381000 },
 135                 { 0x5000, 0x00000000 },
 136                 { 0x5800, 0x000e0000 },
 137         };
 138
 139         static const struct reg_config gpio_clr[] = {
 140                 { 0x1000, 0x00000000 },
 141                 { 0x2000, 0x04381010 },
 142                 { 0x3000, 0x00000000 },
 143                 { 0x4000, 0x00000000 },
 144                 { 0x5000, 0x00400000 },
 145                 { 0x5400, 0x00000000 },
 146                 { 0x5800, 0x000e0380 },
 147         };
 148
 149         static const u32 gpio_base = 0xe6050000;
 150
 151         unsigned int i;
 152
 153         for (i = 0; i < ARRAY_SIZE(gpio_offs); i++)
 154                 writel(0, gpio_base | 0x20 | gpio_offs[i]);
 155
 156         for (i = 0; i < ARRAY_SIZE(gpio_offs); i++)
 157                 writel(0, gpio_base | 0x00 | gpio_offs[i]);
 158
 159         for (i = 0; i < ARRAY_SIZE(gpio_set); i++)
 160                 writel(gpio_set[i].val, gpio_base | 0x08 | gpio_set[i].off);
 161
 162         for (i = 0; i < ARRAY_SIZE(gpio_clr); i++)
 163                 writel(gpio_clr[i].val, gpio_base | 0x04 | gpio_clr[i].off);
 164 }
 165
 166 static void spl_init_lbsc(void)
 167 {
 168         static const struct reg_config lbsc_config[] = {
 169                 { 0x00, 0x00000020 },
 170                 { 0x08, 0x00002020 },
 171                 { 0x30, 0x2a103320 },
 172                 { 0x38, 0xff70ff70 },
 173         };
 174
 175         static const u16 lbsc_offs[] = {
 176                 0x80, 0x84, 0x88, 0x8c, 0xa0, 0xc0, 0xc4, 0xc8, 0x180
 177         };
 178
 179         static const u32 lbsc_base = 0xfec00200;
 180
 181         unsigned int i;
 182
 183         for (i = 0; i < ARRAY_SIZE(lbsc_config); i++) {
 184                 writel(lbsc_config[i].val,
 185                        lbsc_base | lbsc_config[i].off);
 186                 writel(lbsc_config[i].val,
 187                        lbsc_base | (lbsc_config[i].off + 4));
 188         }
 189
 190         for (i = 0; i < ARRAY_SIZE(lbsc_offs); i++)
 191                 writel(0, lbsc_base | lbsc_offs[i]);
 192 }
 193
 194 static void spl_init_dbsc(void)
 195 {
 196         static const struct reg_config dbsc_config1[] = {
 197                 { 0x0280, 0x0000a55a },
 198                 { 0x4000, 0x0000a55a },
 199                 { 0x4008, 0x00000001 },
 200                 { 0x0018, 0x21000000 },
 201                 { 0x0018, 0x11000000 },
 202                 { 0x0018, 0x10000000 },
 203                 { 0x0290, 0x00000001 },
 204                 { 0x02a0, 0x80000000 },
 205                 { 0x0290, 0x00000004 },
 206         };
 207
 208         static const struct reg_config dbsc_config2[] = {
 209                 { 0x0290, 0x00000006 },
 210                 { 0x02a0, 0x0001c000 },
 211         };
 212
 213         static const struct reg_config dbsc_config3r0d0[] = {
 214                 { 0x0290, 0x0000000f },
 215                 { 0x02a0, 0x00181885 },
 216                 { 0x0290, 0x00000070 },
 217                 { 0x02a0, 0x7c000887 },
 218                 { 0x0290, 0x00000080 },
 219                 { 0x02a0, 0x7c000887 },
 220                 { 0x0290, 0x00000090 },
 221                 { 0x02a0, 0x7c000887 },
 222                 { 0x0290, 0x000000a0 },
 223                 { 0x02a0, 0x7c000887 },
 224                 { 0x0290, 0x000000b0 },
 225                 { 0x02a0, 0x7c000880 },
 226                 { 0x0290, 0x000000c0 },
 227                 { 0x02a0, 0x7c000880 },
 228                 { 0x0290, 0x000000d0 },
 229                 { 0x02a0, 0x7c000880 },
 230                 { 0x0290, 0x000000e0 },
 231                 { 0x02a0, 0x7c000880 },
 232         };
 233         static const struct reg_config dbsc_config3r0d1[] = {
 234                 { 0x0290, 0x0000000f },
 235                 { 0x02a0, 0x00181885 },
 236                 { 0x0290, 0x00000070 },
 237                 { 0x02a0, 0x7c000887 },
 238                 { 0x0290, 0x00000080 },
 239                 { 0x02a0, 0x7c000887 },
 240                 { 0x0290, 0x00000090 },
 241                 { 0x02a0, 0x7c000887 },
 242                 { 0x0290, 0x000000a0 },
 243                 { 0x02a0, 0x7c000887 },
 244         };
 245
 246         static const struct reg_config dbsc_config3r2[] = {
 247                 { 0x0290, 0x0000000f },
 248                 { 0x02a0, 0x00181224 },
 249         };
 250
 251         static const struct reg_config dbsc_config4[] = {
 252                 { 0x0290, 0x00000010 },
 253                 { 0x02a0, 0xf004649b },
 254                 { 0x0290, 0x00000061 },
 255                 { 0x02a0, 0x0000006d },
 256                 { 0x0290, 0x00000001 },
 257                 { 0x02a0, 0x00000073 },
 258                 { 0x0020, 0x00000007 },
 259                 { 0x0024, 0x0f030a02 },
 260                 { 0x0030, 0x00000001 },
 261                 { 0x00b0, 0x00000000 },
 262                 { 0x0040, 0x0000000b },
 263                 { 0x0044, 0x00000008 },
 264                 { 0x0048, 0x00000000 },
 265                 { 0x0050, 0x0000000b },
 266                 { 0x0054, 0x000c000b },
 267                 { 0x0058, 0x00000027 },
 268                 { 0x005c, 0x0000001c },
 269                 { 0x0060, 0x00000006 },
 270                 { 0x0064, 0x00000020 },
 271                 { 0x0068, 0x00000008 },
 272                 { 0x006c, 0x0000000c },
 273                 { 0x0070, 0x00000009 },
 274                 { 0x0074, 0x00000012 },
 275                 { 0x0078, 0x000000d0 },
 276                 { 0x007c, 0x00140005 },
 277                 { 0x0080, 0x00050004 },
 278                 { 0x0084, 0x70233005 },
 279                 { 0x0088, 0x000c0000 },
 280                 { 0x008c, 0x00000200 },
 281                 { 0x0090, 0x00000040 },
 282                 { 0x0100, 0x00000001 },
 283                 { 0x00c0, 0x00020001 },
 284                 { 0x00c8, 0x20042004 },
 285                 { 0x0380, 0x00020002 },
 286                 { 0x0390, 0x0000001f },
 287         };
 288
 289         static const struct reg_config dbsc_config5[] = {
 290                 { 0x0244, 0x00000011 },
 291                 { 0x0290, 0x00000003 },
 292                 { 0x02a0, 0x0300c561 },
 293                 { 0x0290, 0x00000023 },
 294                 { 0x02a0, 0x00fcdb60 },
 295                 { 0x0290, 0x00000011 },
 296                 { 0x02a0, 0x1000040b },
 297                 { 0x0290, 0x00000012 },
 298                 { 0x02a0, 0x9d9cbb66 },
 299                 { 0x0290, 0x00000013 },
 300                 { 0x02a0, 0x1a868400 },
 301                 { 0x0290, 0x00000014 },
 302                 { 0x02a0, 0x300214d8 },
 303                 { 0x0290, 0x00000015 },
 304                 { 0x02a0, 0x00000d70 },
 305                 { 0x0290, 0x00000016 },
 306                 { 0x02a0, 0x00000006 },
 307                 { 0x0290, 0x00000017 },
 308                 { 0x02a0, 0x00000018 },
 309                 { 0x0290, 0x0000001a },
 310                 { 0x02a0, 0x910035c7 },
 311                 { 0x0290, 0x00000004 },
 312         };
 313
 314         static const struct reg_config dbsc_config6[] = {
 315                 { 0x0290, 0x00000001 },
 316                 { 0x02a0, 0x00000181 },
 317                 { 0x0018, 0x11000000 },
 318                 { 0x0290, 0x00000004 },
 319         };
 320
 321         static const struct reg_config dbsc_config7[] = {
 322                 { 0x0290, 0x00000001 },
 323                 { 0x02a0, 0x0000fe01 },
 324                 { 0x0304, 0x00000000 },
 325                 { 0x00f4, 0x01004c20 },
 326                 { 0x00f8, 0x014a00b9 },
 327                 { 0x00e0, 0x00000140 },
 328                 { 0x00e4, 0x00081860 },
 329                 { 0x00e8, 0x00010000 },
 330                 { 0x0290, 0x00000004 },
 331         };
 332
 333         static const struct reg_config dbsc_config8[] = {
 334                 { 0x0014, 0x00000001 },
 335                 { 0x0290, 0x00000010 },
 336                 { 0x02a0, 0xf00464db },
 337                 { 0x4008, 0x00000000 },
 338                 { 0x4000, 0x00000000 },
 339                 { 0x0010, 0x00000001 },
 340                 { 0x0280, 0x00000000 },
 341         };
 342
 343         static const u32 dbsc3_0_base = DBSC3_0_BASE;
 344         static const u32 dbsc3_1_base = DBSC3_0_BASE + 0x10000;
 345         static const u32 prr_base = 0xff000044;
 346         const u16 prr_rev = readl(prr_base) & 0x7fff;
 347         unsigned int i;
 348
 349         for (i = 0; i < ARRAY_SIZE(dbsc_config1); i++) {
 350                 writel(dbsc_config1[i].val, dbsc3_0_base | dbsc_config1[i].off);
 351                 writel(dbsc_config1[i].val, dbsc3_1_base | dbsc_config1[i].off);
 352         }
 353
 354         dbsc_wait(0x2a0);
 355
 356         for (i = 0; i < ARRAY_SIZE(dbsc_config2); i++) {
 357                 writel(dbsc_config2[i].val, dbsc3_0_base | dbsc_config2[i].off);
 358                 writel(dbsc_config2[i].val, dbsc3_1_base | dbsc_config2[i].off);
 359         }
 360
 361         if (prr_rev == 0x4700) {
 362                 for (i = 0; i < ARRAY_SIZE(dbsc_config3r0d0); i++) {
 363                         writel(dbsc_config3r0d0[i].val,
 364                                 dbsc3_0_base | dbsc_config3r0d0[i].off);
 365                 }
 366                 for (i = 0; i < ARRAY_SIZE(dbsc_config3r0d1); i++) {
 367                         writel(dbsc_config3r0d1[i].val,
 368                                 dbsc3_1_base | dbsc_config3r0d1[i].off);
 369                 }
 370         } else if (prr_rev != 0x4710) {
 371                 for (i = 0; i < ARRAY_SIZE(dbsc_config3r2); i++) {
 372                         writel(dbsc_config3r2[i].val,
 373                                 dbsc3_0_base | dbsc_config3r2[i].off);
 374                         writel(dbsc_config3r2[i].val,
 375                                 dbsc3_1_base | dbsc_config3r2[i].off);
 376                 }
 377         }
 378
 379         for (i = 0; i < ARRAY_SIZE(dbsc_config4); i++) {
 380                 writel(dbsc_config4[i].val, dbsc3_0_base | dbsc_config4[i].off);
 381                 writel(dbsc_config4[i].val, dbsc3_1_base | dbsc_config4[i].off);
 382         }
 383
 384         dbsc_wait(0x240);
 385
 386         for (i = 0; i < ARRAY_SIZE(dbsc_config5); i++) {
 387                 writel(dbsc_config5[i].val, dbsc3_0_base | dbsc_config5[i].off);
 388                 writel(dbsc_config5[i].val, dbsc3_1_base | dbsc_config5[i].off);
 389         }
 390
 391         dbsc_wait(0x2a0);
 392
 393         for (i = 0; i < ARRAY_SIZE(dbsc_config6); i++) {
 394                 writel(dbsc_config6[i].val, dbsc3_0_base | dbsc_config6[i].off);
 395                 writel(dbsc_config6[i].val, dbsc3_1_base | dbsc_config6[i].off);
 396         }
 397
 398         dbsc_wait(0x2a0);
 399
 400         for (i = 0; i < ARRAY_SIZE(dbsc_config7); i++) {
 401                 writel(dbsc_config7[i].val, dbsc3_0_base | dbsc_config7[i].off);
 402                 writel(dbsc_config7[i].val, dbsc3_1_base | dbsc_config7[i].off);
 403         }
 404
 405         dbsc_wait(0x2a0);
 406
 407         for (i = 0; i < ARRAY_SIZE(dbsc_config8); i++) {
 408                 writel(dbsc_config8[i].val, dbsc3_0_base | dbsc_config8[i].off);
 409                 writel(dbsc_config8[i].val, dbsc3_1_base | dbsc_config8[i].off);
 410         }
 411
 412 }
 413
 414 static void spl_init_qspi(void)
 415 {
 416         mstp_clrbits_le32(MSTPSR9, SMSTPCR9, QSPI_MSTP917);
 417
 418         static const u32 qspi_base = 0xe6b10000;
 419
 420         writeb(0x08, qspi_base + 0x00);
 421         writeb(0x00, qspi_base + 0x01);
 422         writeb(0x06, qspi_base + 0x02);
 423         writeb(0x01, qspi_base + 0x0a);
 424         writeb(0x00, qspi_base + 0x0b);
 425         writeb(0x00, qspi_base + 0x0c);
 426         writeb(0x00, qspi_base + 0x0d);
 427         writeb(0x00, qspi_base + 0x0e);
 428
 429         writew(0xe080, qspi_base + 0x10);
 430
 431         writeb(0xc0, qspi_base + 0x18);
 432         writeb(0x00, qspi_base + 0x18);
 433         writeb(0x00, qspi_base + 0x08);
 434         writeb(0x48, qspi_base + 0x00);
 435 }
 436
 437 void board_init_f(ulong dummy)
 438 {
 439         mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
 440         mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP721);
 441
 442         /*
 443          * SD0 clock is set to 97.5MHz by default.
 444          * Set SD2 to the 97.5MHz as well.
 445          */
 446         writel(SD_97500KHZ, SD2CKCR);
 447
 448         spl_init_sys();
 449         spl_init_pfc();
 450         spl_init_gpio();
 451         spl_init_lbsc();
 452         spl_init_dbsc();
 453         spl_init_qspi();
 454 }
 455
 456 void spl_board_init(void)
 457 {
 458         /* UART clocks enabled and gd valid - init serial console */
 459         preloader_console_init();
 460 }
 461
 462 void board_boot_order(u32 *spl_boot_list)
 463 {
 464         const u32 jtag_magic = 0x1337c0de;
 465         const u32 load_magic = 0xb33fc0de;
 466
 467         /*
 468          * If JTAG probe sets special word at 0xe6300020, then it must
 469          * put U-Boot into RAM and SPL will start it from RAM.
 470          */
 471         if (readl(CONFIG_SPL_TEXT_BASE + 0x20) == jtag_magic) {
 472                 printf("JTAG boot detected!\n");
 473
 474                 while (readl(CONFIG_SPL_TEXT_BASE + 0x24) != load_magic)
 475                         ;
 476
 477                 spl_boot_list[0] = BOOT_DEVICE_RAM;
 478                 spl_boot_list[1] = BOOT_DEVICE_NONE;
 479
 480                 return;
 481         }
 482
 483         /* Boot from SPI NOR with YMODEM UART fallback. */
 484         spl_boot_list[0] = BOOT_DEVICE_SPI;
 485         spl_boot_list[1] = BOOT_DEVICE_UART;
 486         spl_boot_list[2] = BOOT_DEVICE_NONE;
 487 }
 488
 489 void reset_cpu(ulong addr)
 490 {
 491 }