2 * board/renesas/gose/gose.c
4 * Copyright (C) 2014 Renesas Electronics Corporation
6 * SPDX-License-Identifier: GPL-2.0
11 #include <asm/processor.h>
12 #include <asm/mach-types.h>
14 #include <asm/errno.h>
15 #include <asm/arch/sys_proto.h>
17 #include <asm/arch/rmobile.h>
23 DECLARE_GLOBAL_DATA_PTR;
25 #define CLK2MHZ(clk) (clk / 1000 / 1000)
28 struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
29 struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
33 writel(0xA5A5A500, &rwdt->rwtcsra);
34 writel(0xA5A5A500, &swdt->swtcsra);
36 /* CPU frequency setting. Set to 1.5GHz */
37 stc = ((1500 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1) << PLL0_STC_BIT;
38 clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc);
44 #define TMU0_MSTP125 (1 << 25)
45 #define SCIF0_MSTP721 (1 << 21)
46 #define ETHER_MSTP813 (1 << 13)
48 #define mstp_setbits(type, addr, saddr, set) \
49 out_##type((saddr), in_##type(addr) | (set))
50 #define mstp_clrbits(type, addr, saddr, clear) \
51 out_##type((saddr), in_##type(addr) & ~(clear))
52 #define mstp_setbits_le32(addr, saddr, set) \
53 mstp_setbits(le32, addr, saddr, set)
54 #define mstp_clrbits_le32(addr, saddr, clear) \
55 mstp_clrbits(le32, addr, saddr, clear)
57 int board_early_init_f(void)
60 mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
63 mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP721);
66 mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHER_MSTP813);
72 #define TSTR0_STR0 0x01
73 void arch_preboot_os(void)
76 mstp_clrbits_le32(TMU_BASE + TSTR0, TMU_BASE + TSTR0, TSTR0_STR0);
78 mstp_setbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
81 #define PUPR5 0xE6060114
82 #define PUPR5_ETH 0x3FFC0000
83 #define PUPR5_ETH_MAGIC (1 << 27)
87 /* adress of boot parameters */
88 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
90 /* Init PFC controller */
91 r8a7793_pinmux_init();
94 gpio_request(GPIO_FN_ETH_CRS_DV, NULL);
95 gpio_request(GPIO_FN_ETH_RX_ER, NULL);
96 gpio_request(GPIO_FN_ETH_RXD0, NULL);
97 gpio_request(GPIO_FN_ETH_RXD1, NULL);
98 gpio_request(GPIO_FN_ETH_LINK, NULL);
99 gpio_request(GPIO_FN_ETH_REFCLK, NULL);
100 gpio_request(GPIO_FN_ETH_MDIO, NULL);
101 gpio_request(GPIO_FN_ETH_TXD1, NULL);
102 gpio_request(GPIO_FN_ETH_TX_EN, NULL);
103 gpio_request(GPIO_FN_ETH_TXD0, NULL);
104 gpio_request(GPIO_FN_ETH_MDC, NULL);
105 gpio_request(GPIO_FN_IRQ0, NULL);
107 mstp_clrbits_le32(PUPR5, PUPR5, PUPR5_ETH & ~PUPR5_ETH_MAGIC);
108 gpio_request(GPIO_GP_5_22, NULL); /* PHY_RST */
109 mstp_clrbits_le32(PUPR5, PUPR5, PUPR5_ETH_MAGIC);
111 gpio_direction_output(GPIO_GP_5_22, 0);
113 gpio_set_value(GPIO_GP_5_22, 1);
119 #define CXR24 0xEE7003C0 /* MAC address high register */
120 #define CXR25 0xEE7003C8 /* MAC address low register */
122 int board_eth_init(bd_t *bis)
126 unsigned char enetaddr[6];
128 #ifdef CONFIG_SH_ETHER
129 ret = sh_eth_initialize(bis);
130 if (!eth_getenv_enetaddr("ethaddr", enetaddr))
133 /* Set Mac address */
134 val = enetaddr[0] << 24 | enetaddr[1] << 16 |
135 enetaddr[2] << 8 | enetaddr[3];
138 val = enetaddr[4] << 8 | enetaddr[5];
147 gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
152 const struct rmobile_sysinfo sysinfo = {
153 CONFIG_RMOBILE_BOARD_STRING
156 void reset_cpu(ulong addr)
160 i2c_set_bus_num(2); /* PowerIC connected to ch2 */
161 i2c_read(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1);
163 i2c_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1);