2 * board/renesas/eagle/eagle.c
3 * This file is Eagle board support.
5 * Copyright (C) 2017 Marek Vasut <marek.vasut+renesas@gmail.com>
7 * SPDX-License-Identifier: GPL-2.0+
14 #include <dm/platform_data/serial_sh.h>
15 #include <asm/processor.h>
16 #include <asm/mach-types.h>
18 #include <linux/errno.h>
19 #include <asm/arch/sys_proto.h>
21 #include <asm/arch/gpio.h>
22 #include <asm/arch/rmobile.h>
23 #include <asm/arch/rcar-mstp.h>
24 #include <asm/arch/sh_sdhi.h>
28 DECLARE_GLOBAL_DATA_PTR;
30 #define CPGWPCR 0xE6150904
31 #define CPGWPR 0xE615090C
34 #define PLL0CR 0xE61500D8
35 #define PLL0_STC_MASK 0x7F000000
36 #define PLL0_STC_OFFSET 24
38 #define CLK2MHZ(clk) (clk / 1000 / 1000)
41 struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
42 struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
46 writel(0xA5A5A500, &rwdt->rwtcsra);
47 writel(0xA5A5A500, &swdt->swtcsra);
49 /* CPU frequency setting. Set to 0.8GHz */
50 stc = ((800 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1) << PLL0_STC_OFFSET;
51 clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc);
54 #define TMU0_MSTP125 BIT(25) /* secure */
56 int board_early_init_f(void)
58 writel(0xA5A5FFFF, CPGWPCR);
59 writel(0x5A5A0000, CPGWPR);
62 mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
69 /* adress of boot parameters */
70 gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000;
77 if (fdtdec_setup_memory_size() != 0)
83 int dram_init_banksize(void)
85 fdtdec_setup_memory_banksize();
90 #define RST_BASE 0xE6160000
91 #define RST_CA57RESCNT (RST_BASE + 0x40)
92 #define RST_CA53RESCNT (RST_BASE + 0x44)
93 #define RST_RSTOUTCR (RST_BASE + 0x58)
94 #define RST_CA57_CODE 0xA5A5000F
95 #define RST_CA53_CODE 0x5A5A000F
97 void reset_cpu(ulong addr)
99 unsigned long midr, cputype;
101 asm volatile("mrs %0, midr_el1" : "=r" (midr));
102 cputype = (midr >> 4) & 0xfff;
104 if (cputype == 0xd03)
105 writel(RST_CA53_CODE, RST_CA53RESCNT);
106 else if (cputype == 0xd07)
107 writel(RST_CA57_CODE, RST_CA57RESCNT);