2 * board/renesas/blanche/blanche.c
3 * This file is blanche board support.
5 * Copyright (C) 2016 Renesas Electronics Corporation
7 * SPDX-License-Identifier: GPL-2.0
14 #include <dm/platform_data/serial_sh.h>
15 #include <asm/processor.h>
16 #include <asm/mach-types.h>
18 #include <linux/errno.h>
19 #include <asm/arch/sys_proto.h>
21 #include <asm/arch/rmobile.h>
22 #include <asm/arch/rcar-mstp.h>
23 #include <asm/arch/mmc.h>
24 #include <asm/arch/sh_sdhi.h>
30 DECLARE_GLOBAL_DATA_PTR;
33 u32 addr; /* register address */
34 u32 mask; /* mask value */
35 u32 val; /* setting value */
38 #define PMMR 0xE6060000
39 #define GPSR0 0xE6060004
40 #define GPSR1 0xE6060008
41 #define GPSR4 0xE6060014
42 #define GPSR5 0xE6060018
43 #define GPSR6 0xE606001C
44 #define GPSR7 0xE6060020
45 #define GPSR8 0xE6060024
46 #define GPSR9 0xE6060028
47 #define GPSR10 0xE606002C
48 #define GPSR11 0xE6060030
49 #define IPSR6 0xE6060058
50 #define PUPR2 0xE6060108
51 #define PUPR3 0xE606010C
52 #define PUPR4 0xE6060110
53 #define PUPR5 0xE6060114
54 #define PUPR7 0xE606011C
55 #define PUPR9 0xE6060124
56 #define PUPR10 0xE6060128
57 #define PUPR11 0xE606012C
59 #define CPG_PLL1CR 0xE6150028
60 #define CPG_PLL3CR 0xE61500DC
63 writel((readl((x)->addr) & ~((x)->mask)) | ((x)->val), (x)->addr)
65 #define SetGuardREG(x) \
68 val = (readl((x)->addr) & ~((x)->mask)) | ((x)->val); \
70 writel(val, (x)->addr); \
73 struct pin_db pin_guard[] = {
74 { GPSR0, 0xFFFFFFFF, 0x0BFFFFFF },
75 { GPSR1, 0xFFFFFFFF, 0x002FFFFF },
76 { GPSR4, 0xFFFFFFFF, 0x00000FFF },
77 { GPSR5, 0xFFFFFFFF, 0x00010FFF },
78 { GPSR6, 0xFFFFFFFF, 0x00010FFF },
79 { GPSR7, 0xFFFFFFFF, 0x00010FFF },
80 { GPSR8, 0xFFFFFFFF, 0x00010FFF },
81 { GPSR9, 0xFFFFFFFF, 0x00010FFF },
82 { GPSR10, 0xFFFFFFFF, 0x04006000 },
83 { GPSR11, 0xFFFFFFFF, 0x303FEFE0 },
84 { IPSR6, 0xFFFFFFFF, 0x0002000E },
87 struct pin_db pin_tbl[] = {
88 { PUPR2, 0xFFFFFFFF, 0x00000000 },
89 { PUPR3, 0xFFFFFFFF, 0x0803FF40 },
90 { PUPR4, 0xFFFFFFFF, 0x0000FFFF },
91 { PUPR5, 0xFFFFFFFF, 0x00010FFF },
92 { PUPR7, 0xFFFFFFFF, 0x0001AFFF },
93 { PUPR9, 0xFFFFFFFF, 0x0001CFFF },
94 { PUPR10, 0xFFFFFFFF, 0xC0438001 },
95 { PUPR11, 0xFFFFFFFF, 0x0FC00007 },
102 for (db = pin_guard; db < &pin_guard[sizeof(pin_guard)/sizeof(struct pin_db)]; db++) {
105 for (db = pin_tbl; db < &pin_tbl[sizeof(pin_tbl) /sizeof(struct pin_db)]; db++) {
110 #define s_init_wait(cnt) \
112 volatile u32 i = 0x10000 * cnt; \
119 struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
120 struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
123 cpu_type = rmobile_get_cpu_type();
124 if (cpu_type == 0x4A) {
125 writel(0x4D000000, CPG_PLL1CR);
126 writel(0x4F000000, CPG_PLL3CR);
130 writel(0xA5A5A500, &rwdt->rwtcsra);
131 writel(0xA5A5A500, &swdt->swtcsra);
133 /* QoS(Quality-of-Service) Init */
139 #if defined(CONFIG_MTD_NOR_FLASH)
140 struct rcar_lbsc *lbsc = (struct rcar_lbsc *)LBSC_BASE;
141 struct rcar_dbsc3 *dbsc3_0 = (struct rcar_dbsc3 *)DBSC3_0_BASE;
144 writel(0x00000020, &lbsc->cs0ctrl);
145 writel(0x00000020, &lbsc->cs1ctrl);
146 writel(0x00002020, &lbsc->ecs0ctrl);
147 writel(0x00002020, &lbsc->ecs1ctrl);
149 writel(0x2A103320, &lbsc->cswcr0);
150 writel(0x2A103320, &lbsc->cswcr1);
151 writel(0x19102110, &lbsc->ecswcr0);
152 writel(0x19102110, &lbsc->ecswcr1);
157 writel(0x0000A55A, &dbsc3_0->dbpdlck);
159 writel(0x21000000, &dbsc3_0->dbcmd); /* opc=RstH (RESET => H) */
160 writel(0x11000000, &dbsc3_0->dbcmd); /* opc=PDXt(CKE=H) */
161 writel(0x10000000, &dbsc3_0->dbcmd); /* opc=PDEn(CKE=L) */
163 /* Stop Auto-Calibration */
164 writel(0x00000001, &dbsc3_0->dbpdrga);
165 writel(0x80000000, &dbsc3_0->dbpdrgd);
167 writel(0x00000004, &dbsc3_0->dbpdrga);
168 while ((readl(&dbsc3_0->dbpdrgd) & 0x00000001) != 0x00000001);
170 /* PLLCR: PLL Control Register */
171 writel(0x00000006, &dbsc3_0->dbpdrga);
172 writel(0x0001C000, &dbsc3_0->dbpdrgd); // > DDR1440
174 /* DXCCR: DATX8 Common Configuration Register */
175 writel(0x0000000F, &dbsc3_0->dbpdrga);
176 writel(0x00181EE4, &dbsc3_0->dbpdrgd);
178 /* DSGCR :DDR System General Configuration Register */
179 writel(0x00000010, &dbsc3_0->dbpdrga);
180 writel(0xF00464DB, &dbsc3_0->dbpdrgd);
182 writel(0x00000061, &dbsc3_0->dbpdrga);
183 writel(0x0000008D, &dbsc3_0->dbpdrgd);
185 /* Re-Execute ZQ calibration */
186 writel(0x00000001, &dbsc3_0->dbpdrga);
187 writel(0x00000073, &dbsc3_0->dbpdrgd);
189 writel(0x00000007, &dbsc3_0->dbkind);
190 writel(0x0F030A02, &dbsc3_0->dbconf0);
191 writel(0x00000001, &dbsc3_0->dbphytype);
192 writel(0x00000000, &dbsc3_0->dbbl);
194 writel(0x0000000B, &dbsc3_0->dbtr0); // tCL=11
195 writel(0x00000008, &dbsc3_0->dbtr1); // tCWL=8
196 writel(0x00000000, &dbsc3_0->dbtr2); // tAL=0
197 writel(0x0000000B, &dbsc3_0->dbtr3); // tRCD=11
198 writel(0x000C000B, &dbsc3_0->dbtr4); // tRPA=12,tRP=11
199 writel(0x00000027, &dbsc3_0->dbtr5); // tRC = 39
200 writel(0x0000001C, &dbsc3_0->dbtr6); // tRAS = 28
201 writel(0x00000006, &dbsc3_0->dbtr7); // tRRD = 6
202 writel(0x00000020, &dbsc3_0->dbtr8); // tRFAW = 32
203 writel(0x00000008, &dbsc3_0->dbtr9); // tRDPR = 8
204 writel(0x0000000C, &dbsc3_0->dbtr10); // tWR = 12
205 writel(0x00000009, &dbsc3_0->dbtr11); // tRDWR = 9
206 writel(0x00000012, &dbsc3_0->dbtr12); // tWRRD = 18
207 writel(0x000000D0, &dbsc3_0->dbtr13); // tRFC = 208
208 writel(0x00140005, &dbsc3_0->dbtr14);
209 writel(0x00050004, &dbsc3_0->dbtr15);
210 writel(0x70233005, &dbsc3_0->dbtr16); /* DQL = 35, WDQL = 5 */
211 writel(0x000C0000, &dbsc3_0->dbtr17);
212 writel(0x00000300, &dbsc3_0->dbtr18);
213 writel(0x00000040, &dbsc3_0->dbtr19);
214 writel(0x00000001, &dbsc3_0->dbrnk0);
215 writel(0x00020001, &dbsc3_0->dbadj0);
216 writel(0x20082004, &dbsc3_0->dbadj2); /* blanche QoS rev0.1 */
217 writel(0x00020002, &dbsc3_0->dbwt0cnf0); /* 1600 */
218 writel(0x0000001F, &dbsc3_0->dbwt0cnf4);
220 while ((readl(&dbsc3_0->dbdfistat) & 0x00000001) != 0x00000001);
221 writel(0x00000011, &dbsc3_0->dbdficnt);
223 /* PGCR1 :PHY General Configuration Register 1 */
224 writel(0x00000003, &dbsc3_0->dbpdrga);
225 writel(0x0300C4E1, &dbsc3_0->dbpdrgd); /* DDR3 */
227 /* PGCR2: PHY General Configuration Registers 2 */
228 writel(0x00000023, &dbsc3_0->dbpdrga);
229 writel(0x00FCDB60, &dbsc3_0->dbpdrgd);
231 writel(0x00000011, &dbsc3_0->dbpdrga);
232 writel(0x1000040B, &dbsc3_0->dbpdrgd);
234 /* DTPR0 :DRAM Timing Parameters Register 0 */
235 writel(0x00000012, &dbsc3_0->dbpdrga);
236 writel(0x9D9CBB66, &dbsc3_0->dbpdrgd);
238 /* DTPR1 :DRAM Timing Parameters Register 1 */
239 writel(0x00000013, &dbsc3_0->dbpdrga);
240 writel(0x1A868400, &dbsc3_0->dbpdrgd);
242 /* DTPR2 ::DRAM Timing Parameters Register 2 */
243 writel(0x00000014, &dbsc3_0->dbpdrga);
244 writel(0x300214D8, &dbsc3_0->dbpdrgd);
246 /* MR0 :Mode Register 0 */
247 writel(0x00000015, &dbsc3_0->dbpdrga);
248 writel(0x00000D70, &dbsc3_0->dbpdrgd);
250 /* MR1 :Mode Register 1 */
251 writel(0x00000016, &dbsc3_0->dbpdrga);
252 writel(0x00000004, &dbsc3_0->dbpdrgd); /* DRAM Drv 40ohm */
254 /* MR2 :Mode Register 2 */
255 writel(0x00000017, &dbsc3_0->dbpdrga);
256 writel(0x00000018, &dbsc3_0->dbpdrgd); /* CWL=8 */
259 writel(0x0000001A, &dbsc3_0->dbpdrga);
260 writel(0x910035C7, &dbsc3_0->dbpdrgd);
262 /* PGSR0 :PHY General Status Registers 0 */
263 writel(0x00000004, &dbsc3_0->dbpdrga);
264 while ((readl(&dbsc3_0->dbpdrgd) & 0x00000001) != 0x00000001);
266 /* DRAM Init (set MRx etc) */
267 writel(0x00000001, &dbsc3_0->dbpdrga);
268 writel(0x00000181, &dbsc3_0->dbpdrgd);
271 writel(0x11000000, &dbsc3_0->dbcmd); /* opc=PDXt(CKE=H) */
273 /* PGSR0 :PHY General Status Registers 0 */
274 writel(0x00000004, &dbsc3_0->dbpdrga);
275 while ((readl(&dbsc3_0->dbpdrgd) & 0x00000001) != 0x00000001);
277 /* RAM ACC Training */
278 writel(0x00000001, &dbsc3_0->dbpdrga);
279 writel(0x0000FE01, &dbsc3_0->dbpdrgd);
282 writel(0x00000000, &dbsc3_0->dbbs0cnt1);
283 /* DDR3 Calibration set */
284 writel(0x01004C20, &dbsc3_0->dbcalcnf);
285 /* DDR3 Calibration timing */
286 writel(0x014000AA, &dbsc3_0->dbcaltr);
288 writel(0x00000140, &dbsc3_0->dbrfcnf0);
289 writel(0x00081860, &dbsc3_0->dbrfcnf1);
290 writel(0x00010000, &dbsc3_0->dbrfcnf2);
292 /* PGSR0 :PHY General Status Registers 0 */
293 writel(0x00000004, &dbsc3_0->dbpdrga);
294 while ((readl(&dbsc3_0->dbpdrgd) & 0x00000001) != 0x00000001);
296 /* Enable Auto-Refresh */
297 writel(0x00000001, &dbsc3_0->dbrfen);
298 /* Permit DDR-Access */
299 writel(0x00000001, &dbsc3_0->dbacen);
301 /* This locks the access to the PHY unit registers */
302 writel(0x00000000, &dbsc3_0->dbpdlck);
303 #endif /* CONFIG_MTD_NOR_FLASH */
307 #define TMU0_MSTP125 (1 << 25)
308 #define SCIF0_MSTP721 (1 << 21)
309 #define SDHI0_MSTP314 (1 << 14)
310 #define QSPI_MSTP917 (1 << 17)
312 int board_early_init_f(void)
315 mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
317 mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP721);
319 mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SDHI0_MSTP314);
321 mstp_clrbits_le32(MSTPSR9, SMSTPCR9, QSPI_MSTP917);
326 DECLARE_GLOBAL_DATA_PTR;
329 /* adress of boot parameters */
330 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
332 /* Init PFC controller */
333 r8a7792_pinmux_init();
335 gpio_request(GPIO_FN_D0, NULL);
336 gpio_request(GPIO_FN_D1, NULL);
337 gpio_request(GPIO_FN_D2, NULL);
338 gpio_request(GPIO_FN_D3, NULL);
339 gpio_request(GPIO_FN_D4, NULL);
340 gpio_request(GPIO_FN_D5, NULL);
341 gpio_request(GPIO_FN_D6, NULL);
342 gpio_request(GPIO_FN_D7, NULL);
343 gpio_request(GPIO_FN_D8, NULL);
344 gpio_request(GPIO_FN_D9, NULL);
345 gpio_request(GPIO_FN_D10, NULL);
346 gpio_request(GPIO_FN_D11, NULL);
347 gpio_request(GPIO_FN_D12, NULL);
348 gpio_request(GPIO_FN_D13, NULL);
349 gpio_request(GPIO_FN_D14, NULL);
350 gpio_request(GPIO_FN_D15, NULL);
351 gpio_request(GPIO_FN_A0, NULL);
352 gpio_request(GPIO_FN_A1, NULL);
353 gpio_request(GPIO_FN_A2, NULL);
354 gpio_request(GPIO_FN_A3, NULL);
355 gpio_request(GPIO_FN_A4, NULL);
356 gpio_request(GPIO_FN_A5, NULL);
357 gpio_request(GPIO_FN_A6, NULL);
358 gpio_request(GPIO_FN_A7, NULL);
359 gpio_request(GPIO_FN_A8, NULL);
360 gpio_request(GPIO_FN_A9, NULL);
361 gpio_request(GPIO_FN_A10, NULL);
362 gpio_request(GPIO_FN_A11, NULL);
363 gpio_request(GPIO_FN_A12, NULL);
364 gpio_request(GPIO_FN_A13, NULL);
365 gpio_request(GPIO_FN_A14, NULL);
366 gpio_request(GPIO_FN_A15, NULL);
367 gpio_request(GPIO_FN_A16, NULL);
368 gpio_request(GPIO_FN_A17, NULL);
369 gpio_request(GPIO_FN_A18, NULL);
370 gpio_request(GPIO_FN_A19, NULL);
371 #if !defined(CONFIG_MTD_NOR_FLASH)
372 gpio_request(GPIO_FN_MOSI_IO0, NULL);
373 gpio_request(GPIO_FN_MISO_IO1, NULL);
374 gpio_request(GPIO_FN_IO2, NULL);
375 gpio_request(GPIO_FN_IO3, NULL);
376 gpio_request(GPIO_FN_SPCLK, NULL);
377 gpio_request(GPIO_FN_SSL, NULL);
378 #else /* CONFIG_MTD_NOR_FLASH */
379 gpio_request(GPIO_FN_A20, NULL);
380 gpio_request(GPIO_FN_A21, NULL);
381 gpio_request(GPIO_FN_A22, NULL);
382 gpio_request(GPIO_FN_A23, NULL);
383 gpio_request(GPIO_FN_A24, NULL);
384 gpio_request(GPIO_FN_A25, NULL);
385 #endif /* CONFIG_MTD_NOR_FLASH */
387 gpio_request(GPIO_FN_CS1_A26, NULL);
388 gpio_request(GPIO_FN_EX_CS0, NULL);
389 gpio_request(GPIO_FN_EX_CS1, NULL);
390 gpio_request(GPIO_FN_BS, NULL);
391 gpio_request(GPIO_FN_RD, NULL);
392 gpio_request(GPIO_FN_WE0, NULL);
393 gpio_request(GPIO_FN_WE1, NULL);
394 gpio_request(GPIO_FN_EX_WAIT0, NULL);
395 gpio_request(GPIO_FN_IRQ0, NULL);
396 gpio_request(GPIO_FN_IRQ2, NULL);
397 gpio_request(GPIO_FN_IRQ3, NULL);
398 gpio_request(GPIO_FN_CS0, NULL);
407 Added for BLANCHE(R-CarV2H board)
409 int board_eth_init(bd_t *bis)
413 #ifdef CONFIG_SMC911X
414 #define STR_ENV_ETHADDR "ethaddr"
416 struct eth_device *dev;
419 rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
421 if (!eth_env_get_enetaddr(STR_ENV_ETHADDR, eth_addr)) {
422 dev = eth_get_dev_by_index(0);
424 eth_env_set_enetaddr(STR_ENV_ETHADDR, dev->enetaddr);
426 printf("blanche: Couldn't get eth device\n");
436 int board_mmc_init(bd_t *bis)
440 #ifdef CONFIG_SH_SDHI
441 gpio_request(GPIO_FN_SD0_DAT0, NULL);
442 gpio_request(GPIO_FN_SD0_DAT1, NULL);
443 gpio_request(GPIO_FN_SD0_DAT2, NULL);
444 gpio_request(GPIO_FN_SD0_DAT3, NULL);
445 gpio_request(GPIO_FN_SD0_CLK, NULL);
446 gpio_request(GPIO_FN_SD0_CMD, NULL);
447 gpio_request(GPIO_FN_SD0_CD, NULL);
449 gpio_request(GPIO_GP_11_12, NULL);
450 gpio_direction_output(GPIO_GP_11_12, 1); /* power on */
453 ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI0_BASE, 0,
454 SH_SDHI_QUIRK_16BIT_BUF);
464 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
465 gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
470 const struct rmobile_sysinfo sysinfo = {
471 CONFIG_RMOBILE_BOARD_STRING
474 void reset_cpu(ulong addr)
478 static const struct sh_serial_platdata serial_platdata = {
485 U_BOOT_DEVICE(blanche_serials) = {
487 .platdata = &serial_platdata,