2 * board/renesas/blanche/blanche.c
3 * This file is blanche board support.
5 * Copyright (C) 2016 Renesas Electronics Corporation
7 * SPDX-License-Identifier: GPL-2.0
14 #include <dm/platform_data/serial_sh.h>
15 #include <asm/processor.h>
16 #include <asm/mach-types.h>
18 #include <asm/errno.h>
19 #include <asm/arch/sys_proto.h>
21 #include <asm/arch/rmobile.h>
22 #include <asm/arch/rcar-mstp.h>
23 #include <asm/arch/mmc.h>
24 #include <asm/arch/sh_sdhi.h>
30 DECLARE_GLOBAL_DATA_PTR;
33 u32 addr; /* register address */
34 u32 mask; /* mask value */
35 u32 val; /* setting value */
38 #define PMMR 0xE6060000
39 #define GPSR10 0xE606002C
40 #define PUPR3 0xE606010C
41 #define PUPR10 0xE6060128
42 #define PUPR11 0xE606012C
44 #define CPG_PLL1CR 0xE6150028
45 #define CPG_PLL3CR 0xE61500DC
48 writel((readl((x)->addr) & ~((x)->mask)) | ((x)->val), (x)->addr)
50 #define SetGuardREG(x) \
53 val = (readl((x)->addr) & ~((x)->mask)) | ((x)->val); \
55 writel(val, (x)->addr); \
58 struct pin_db pin_guard[] = {
59 { GPSR10, 0xFFFFFFFF, 0x04006000 },
62 struct pin_db pin_tbl[] = {
63 { PUPR3, 0xFFFFFFFF, 0x0803FF40 },
64 { PUPR10, 0xFFFFFFFF, 0xC0438001 },
65 { PUPR11, 0xFFFFFFFF, 0x0FC00007 },
72 for (db = pin_guard; db < &pin_guard[sizeof(pin_guard)/sizeof(struct pin_db)]; db++) {
75 for (db = pin_tbl; db < &pin_tbl[sizeof(pin_tbl) /sizeof(struct pin_db)]; db++) {
80 #define s_init_wait(cnt) \
82 volatile u32 i = 0x10000 * cnt; \
89 struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
90 struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
93 cpu_type = rmobile_get_cpu_type();
94 if (cpu_type == 0x4A) {
95 writel(0x4D000000, CPG_PLL1CR);
96 writel(0x4F000000, CPG_PLL3CR);
100 writel(0xA5A5A500, &rwdt->rwtcsra);
101 writel(0xA5A5A500, &swdt->swtcsra);
103 /* QoS(Quality-of-Service) Init */
109 #if !defined(CONFIG_SYS_NO_FLASH)
110 struct rcar_lbsc *lbsc = (struct rcar_lbsc *)LBSC_BASE;
111 struct rcar_dbsc3 *dbsc3_0 = (struct rcar_dbsc3 *)DBSC3_0_BASE;
114 writel(0x00000020, &lbsc->cs0ctrl);
115 writel(0x00000020, &lbsc->cs1ctrl);
116 writel(0x00002020, &lbsc->ecs0ctrl);
117 writel(0x00002020, &lbsc->ecs1ctrl);
119 writel(0x2A103320, &lbsc->cswcr0);
120 writel(0x2A103320, &lbsc->cswcr1);
121 writel(0x19102110, &lbsc->ecswcr0);
122 writel(0x19102110, &lbsc->ecswcr1);
127 writel(0x0000A55A, &dbsc3_0->dbpdlck);
129 writel(0x21000000, &dbsc3_0->dbcmd); /* opc=RstH (RESET => H) */
130 writel(0x11000000, &dbsc3_0->dbcmd); /* opc=PDXt(CKE=H) */
131 writel(0x10000000, &dbsc3_0->dbcmd); /* opc=PDEn(CKE=L) */
133 /* Stop Auto-Calibration */
134 writel(0x00000001, &dbsc3_0->dbpdrga);
135 writel(0x80000000, &dbsc3_0->dbpdrgd);
137 writel(0x00000004, &dbsc3_0->dbpdrga);
138 while ((readl(&dbsc3_0->dbpdrgd) & 0x00000001) != 0x00000001);
140 /* PLLCR: PLL Control Register */
141 writel(0x00000006, &dbsc3_0->dbpdrga);
142 writel(0x0001C000, &dbsc3_0->dbpdrgd); // > DDR1440
144 /* DXCCR: DATX8 Common Configuration Register */
145 writel(0x0000000F, &dbsc3_0->dbpdrga);
146 writel(0x00181EE4, &dbsc3_0->dbpdrgd);
148 /* DSGCR :DDR System General Configuration Register */
149 writel(0x00000010, &dbsc3_0->dbpdrga);
150 writel(0xF00464DB, &dbsc3_0->dbpdrgd);
152 writel(0x00000061, &dbsc3_0->dbpdrga);
153 writel(0x0000008D, &dbsc3_0->dbpdrgd);
155 /* Re-Execute ZQ calibration */
156 writel(0x00000001, &dbsc3_0->dbpdrga);
157 writel(0x00000073, &dbsc3_0->dbpdrgd);
159 writel(0x00000007, &dbsc3_0->dbkind);
160 writel(0x0F030A02, &dbsc3_0->dbconf0);
161 writel(0x00000001, &dbsc3_0->dbphytype);
162 writel(0x00000000, &dbsc3_0->dbbl);
164 writel(0x0000000B, &dbsc3_0->dbtr0); // tCL=11
165 writel(0x00000008, &dbsc3_0->dbtr1); // tCWL=8
166 writel(0x00000000, &dbsc3_0->dbtr2); // tAL=0
167 writel(0x0000000B, &dbsc3_0->dbtr3); // tRCD=11
168 writel(0x000C000B, &dbsc3_0->dbtr4); // tRPA=12,tRP=11
169 writel(0x00000027, &dbsc3_0->dbtr5); // tRC = 39
170 writel(0x0000001C, &dbsc3_0->dbtr6); // tRAS = 28
171 writel(0x00000006, &dbsc3_0->dbtr7); // tRRD = 6
172 writel(0x00000020, &dbsc3_0->dbtr8); // tRFAW = 32
173 writel(0x00000008, &dbsc3_0->dbtr9); // tRDPR = 8
174 writel(0x0000000C, &dbsc3_0->dbtr10); // tWR = 12
175 writel(0x00000009, &dbsc3_0->dbtr11); // tRDWR = 9
176 writel(0x00000012, &dbsc3_0->dbtr12); // tWRRD = 18
177 writel(0x000000D0, &dbsc3_0->dbtr13); // tRFC = 208
178 writel(0x00140005, &dbsc3_0->dbtr14);
179 writel(0x00050004, &dbsc3_0->dbtr15);
180 writel(0x70233005, &dbsc3_0->dbtr16); /* DQL = 35, WDQL = 5 */
181 writel(0x000C0000, &dbsc3_0->dbtr17);
182 writel(0x00000300, &dbsc3_0->dbtr18);
183 writel(0x00000040, &dbsc3_0->dbtr19);
184 writel(0x00000001, &dbsc3_0->dbrnk0);
185 writel(0x00020001, &dbsc3_0->dbadj0);
186 writel(0x20082004, &dbsc3_0->dbadj2); /* blanche QoS rev0.1 */
187 writel(0x00020002, &dbsc3_0->dbwt0cnf0); /* 1600 */
188 writel(0x0000001F, &dbsc3_0->dbwt0cnf4);
190 while ((readl(&dbsc3_0->dbdfistat) & 0x00000001) != 0x00000001);
191 writel(0x00000011, &dbsc3_0->dbdficnt);
193 /* PGCR1 :PHY General Configuration Register 1 */
194 writel(0x00000003, &dbsc3_0->dbpdrga);
195 writel(0x0300C4E1, &dbsc3_0->dbpdrgd); /* DDR3 */
197 /* PGCR2: PHY General Configuration Registers 2 */
198 writel(0x00000023, &dbsc3_0->dbpdrga);
199 writel(0x00FCDB60, &dbsc3_0->dbpdrgd);
201 writel(0x00000011, &dbsc3_0->dbpdrga);
202 writel(0x1000040B, &dbsc3_0->dbpdrgd);
204 /* DTPR0 :DRAM Timing Parameters Register 0 */
205 writel(0x00000012, &dbsc3_0->dbpdrga);
206 writel(0x9D9CBB66, &dbsc3_0->dbpdrgd);
208 /* DTPR1 :DRAM Timing Parameters Register 1 */
209 writel(0x00000013, &dbsc3_0->dbpdrga);
210 writel(0x1A868400, &dbsc3_0->dbpdrgd);
212 /* DTPR2 ::DRAM Timing Parameters Register 2 */
213 writel(0x00000014, &dbsc3_0->dbpdrga);
214 writel(0x300214D8, &dbsc3_0->dbpdrgd);
216 /* MR0 :Mode Register 0 */
217 writel(0x00000015, &dbsc3_0->dbpdrga);
218 writel(0x00000D70, &dbsc3_0->dbpdrgd);
220 /* MR1 :Mode Register 1 */
221 writel(0x00000016, &dbsc3_0->dbpdrga);
222 writel(0x00000004, &dbsc3_0->dbpdrgd); /* DRAM Drv 40ohm */
224 /* MR2 :Mode Register 2 */
225 writel(0x00000017, &dbsc3_0->dbpdrga);
226 writel(0x00000018, &dbsc3_0->dbpdrgd); /* CWL=8 */
229 writel(0x0000001A, &dbsc3_0->dbpdrga);
230 writel(0x910035C7, &dbsc3_0->dbpdrgd);
232 /* PGSR0 :PHY General Status Registers 0 */
233 writel(0x00000004, &dbsc3_0->dbpdrga);
234 while ((readl(&dbsc3_0->dbpdrgd) & 0x00000001) != 0x00000001);
236 /* DRAM Init (set MRx etc) */
237 writel(0x00000001, &dbsc3_0->dbpdrga);
238 writel(0x00000181, &dbsc3_0->dbpdrgd);
241 writel(0x11000000, &dbsc3_0->dbcmd); /* opc=PDXt(CKE=H) */
243 /* PGSR0 :PHY General Status Registers 0 */
244 writel(0x00000004, &dbsc3_0->dbpdrga);
245 while ((readl(&dbsc3_0->dbpdrgd) & 0x00000001) != 0x00000001);
247 /* RAM ACC Training */
248 writel(0x00000001, &dbsc3_0->dbpdrga);
249 writel(0x0000FE01, &dbsc3_0->dbpdrgd);
252 writel(0x00000000, &dbsc3_0->dbbs0cnt1);
253 /* DDR3 Calibration set */
254 writel(0x01004C20, &dbsc3_0->dbcalcnf);
255 /* DDR3 Calibration timing */
256 writel(0x014000AA, &dbsc3_0->dbcaltr);
258 writel(0x00000140, &dbsc3_0->dbrfcnf0);
259 writel(0x00081860, &dbsc3_0->dbrfcnf1);
260 writel(0x00010000, &dbsc3_0->dbrfcnf2);
262 /* PGSR0 :PHY General Status Registers 0 */
263 writel(0x00000004, &dbsc3_0->dbpdrga);
264 while ((readl(&dbsc3_0->dbpdrgd) & 0x00000001) != 0x00000001);
266 /* Enable Auto-Refresh */
267 writel(0x00000001, &dbsc3_0->dbrfen);
268 /* Permit DDR-Access */
269 writel(0x00000001, &dbsc3_0->dbacen);
271 /* This locks the access to the PHY unit registers */
272 writel(0x00000000, &dbsc3_0->dbpdlck);
273 #endif /* CONFIG_SYS_NO_FLASH */
277 #define TMU0_MSTP125 (1 << 25)
278 #define SCIF0_MSTP721 (1 << 21)
279 #define SDHI0_MSTP314 (1 << 14)
280 #define QSPI_MSTP917 (1 << 17)
282 int board_early_init_f(void)
285 mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
287 mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP721);
289 mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SDHI0_MSTP314);
291 mstp_clrbits_le32(MSTPSR9, SMSTPCR9, QSPI_MSTP917);
296 DECLARE_GLOBAL_DATA_PTR;
299 /* adress of boot parameters */
300 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
302 /* Init PFC controller */
303 r8a7792_pinmux_init();
305 gpio_request(GPIO_FN_D0, NULL);
306 gpio_request(GPIO_FN_D1, NULL);
307 gpio_request(GPIO_FN_D2, NULL);
308 gpio_request(GPIO_FN_D3, NULL);
309 gpio_request(GPIO_FN_D4, NULL);
310 gpio_request(GPIO_FN_D5, NULL);
311 gpio_request(GPIO_FN_D6, NULL);
312 gpio_request(GPIO_FN_D7, NULL);
313 gpio_request(GPIO_FN_D8, NULL);
314 gpio_request(GPIO_FN_D9, NULL);
315 gpio_request(GPIO_FN_D10, NULL);
316 gpio_request(GPIO_FN_D11, NULL);
317 gpio_request(GPIO_FN_D12, NULL);
318 gpio_request(GPIO_FN_D13, NULL);
319 gpio_request(GPIO_FN_D14, NULL);
320 gpio_request(GPIO_FN_D15, NULL);
321 gpio_request(GPIO_FN_A0, NULL);
322 gpio_request(GPIO_FN_A1, NULL);
323 gpio_request(GPIO_FN_A2, NULL);
324 gpio_request(GPIO_FN_A3, NULL);
325 gpio_request(GPIO_FN_A4, NULL);
326 gpio_request(GPIO_FN_A5, NULL);
327 gpio_request(GPIO_FN_A6, NULL);
328 gpio_request(GPIO_FN_A7, NULL);
329 gpio_request(GPIO_FN_A8, NULL);
330 gpio_request(GPIO_FN_A9, NULL);
331 gpio_request(GPIO_FN_A10, NULL);
332 gpio_request(GPIO_FN_A11, NULL);
333 gpio_request(GPIO_FN_A12, NULL);
334 gpio_request(GPIO_FN_A13, NULL);
335 gpio_request(GPIO_FN_A14, NULL);
336 gpio_request(GPIO_FN_A15, NULL);
337 gpio_request(GPIO_FN_A16, NULL);
338 gpio_request(GPIO_FN_A17, NULL);
339 gpio_request(GPIO_FN_A18, NULL);
340 gpio_request(GPIO_FN_A19, NULL);
341 #if defined(CONFIG_SYS_NO_FLASH)
342 gpio_request(GPIO_FN_MOSI_IO0, NULL);
343 gpio_request(GPIO_FN_MISO_IO1, NULL);
344 gpio_request(GPIO_FN_IO2, NULL);
345 gpio_request(GPIO_FN_IO3, NULL);
346 gpio_request(GPIO_FN_SPCLK, NULL);
347 gpio_request(GPIO_FN_SSL, NULL);
348 #else /* CONFIG_SYS_NO_FLASH */
349 gpio_request(GPIO_FN_A20, NULL);
350 gpio_request(GPIO_FN_A21, NULL);
351 gpio_request(GPIO_FN_A22, NULL);
352 gpio_request(GPIO_FN_A23, NULL);
353 gpio_request(GPIO_FN_A24, NULL);
354 gpio_request(GPIO_FN_A25, NULL);
355 #endif /* CONFIG_SYS_NO_FLASH */
357 gpio_request(GPIO_FN_CS1_A26, NULL);
358 gpio_request(GPIO_FN_EX_CS0, NULL);
359 gpio_request(GPIO_FN_EX_CS1, NULL);
360 gpio_request(GPIO_FN_BS, NULL);
361 gpio_request(GPIO_FN_RD, NULL);
362 gpio_request(GPIO_FN_WE0, NULL);
363 gpio_request(GPIO_FN_WE1, NULL);
364 gpio_request(GPIO_FN_EX_WAIT0, NULL);
365 gpio_request(GPIO_FN_IRQ0, NULL);
366 gpio_request(GPIO_FN_IRQ2, NULL);
367 gpio_request(GPIO_FN_IRQ3, NULL);
368 gpio_request(GPIO_FN_CS0, NULL);
377 Added for BLANCHE(R-CarV2H board)
379 int board_eth_init(bd_t *bis)
383 #ifdef CONFIG_SMC911X
384 #define STR_ENV_ETHADDR "ethaddr"
386 struct eth_device *dev;
389 rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
391 if (!eth_getenv_enetaddr(STR_ENV_ETHADDR, eth_addr)) {
392 dev = eth_get_dev_by_index(0);
394 eth_setenv_enetaddr(STR_ENV_ETHADDR, dev->enetaddr);
396 printf("blanche: Couldn't get eth device\n");
406 int board_mmc_init(bd_t *bis)
410 #ifdef CONFIG_SH_SDHI
411 gpio_request(GPIO_FN_SD0_DAT0, NULL);
412 gpio_request(GPIO_FN_SD0_DAT1, NULL);
413 gpio_request(GPIO_FN_SD0_DAT2, NULL);
414 gpio_request(GPIO_FN_SD0_DAT3, NULL);
415 gpio_request(GPIO_FN_SD0_CLK, NULL);
416 gpio_request(GPIO_FN_SD0_CMD, NULL);
417 gpio_request(GPIO_FN_SD0_CD, NULL);
419 gpio_request(GPIO_GP_11_12, NULL);
420 gpio_direction_output(GPIO_GP_11_12, 1); /* power on */
423 ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI0_BASE, 0,
424 SH_SDHI_QUIRK_16BIT_BUF);
434 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
435 gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
440 const struct rmobile_sysinfo sysinfo = {
441 CONFIG_RMOBILE_BOARD_STRING
444 void reset_cpu(ulong addr)
448 static const struct sh_serial_platdata serial_platdata = {
455 U_BOOT_DEVICE(blanche_serials) = {
457 .platdata = &serial_platdata,