2 * (C) Copyright 2000-2003
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include <asm/m5271.h>
26 #include <asm/immap_5271.h>
29 int checkboard (void) {
30 puts ("Board: R5200 Ethernet Module\n");
34 long int initdram (int board_type) {
38 * Set CS2 pin to be SD_CS0
40 mbar_writeByte(MCF_GPIO_PAR_CS, mbar_readByte(MCF_GPIO_PAR_CS)
41 | MCF_GPIO_PAR_CS_PAR_CS2);
43 mbar_writeByte(MCF_GPIO_PAR_SDRAM, mbar_readByte(MCF_GPIO_PAR_SDRAM)
44 | MCF_GPIO_PAR_SDRAM_PAR_CSSDCS(0x01));
47 * Check to see if the SDRAM has already been initialized
48 * by a run control tool
50 if (!(mbar_readLong(MCF_SDRAMC_DACR0) & MCF_SDRAMC_DACRn_RE))
53 * Initialize DRAM Control Register: DCR
55 mbar_writeShort(MCF_SDRAMC_DCR, MCF_SDRAMC_DCR_RTIM(0x01)
56 | MCF_SDRAMC_DCR_RC(0x30));
61 mbar_writeLong(MCF_SDRAMC_DACR0,
62 MCF_SDRAMC_DACRn_BA(CFG_SDRAM_BASE>>18)
63 | MCF_SDRAMC_DACRn_CASL(0)
64 | MCF_SDRAMC_DACRn_CBM(3)
65 | MCF_SDRAMC_DACRn_PS(2));
70 mbar_writeLong(MCF_SDRAMC_DMR0,
71 MCF_SDRAMC_DMRn_BAM_8M
77 mbar_writeLong(MCF_SDRAMC_DACR0, mbar_readLong(MCF_SDRAMC_DACR0)
78 | MCF_SDRAMC_DACRn_IP);
81 * Wait at least 20ns to allow banks to precharge
83 for (i = 0; i < 5; i++)
87 * Write to this block to initiate precharge
89 *(u16 *)(CFG_SDRAM_BASE) = 0x9696;
94 mbar_writeLong(MCF_SDRAMC_DACR0, mbar_readLong(MCF_SDRAMC_DACR0)
95 | MCF_SDRAMC_DACRn_RE);
99 * Wait for at least 8 auto refresh cycles to occur
101 for (i = 0; i < 2000; i++)
105 * Finish the configuration by issuing the MRS.
107 mbar_writeLong(MCF_SDRAMC_DACR0, mbar_readLong(MCF_SDRAMC_DACR0)
108 | MCF_SDRAMC_DACRn_MRS);
112 * Write to the SDRAM Mode Register
114 *(u16 *)(CFG_SDRAM_BASE + 0x1000) = 0x9696;
117 return CFG_SDRAM_SIZE * 1024 * 1024;
120 int testdram (void) {
121 /* TODO: XXX XXX XXX */
122 printf ("DRAM test not implemented!\n");