1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (c) 2014 DENX
4 * Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr>
6 * Derived from code written by Robert Aigner (ra@spiid.net)
8 * Itself derived from Beagle Board and 3430 SDP code by
9 * Richard Woodruff <r-woodruff2@ti.com>
10 * Syed Mohammed Khasim <khasim@ti.com>
17 #include <asm/arch/mem.h>
18 #include <asm/arch/mux.h>
19 #include <asm/arch/sys_proto.h>
21 #include <asm/mach-types.h>
22 #include <asm/omap_mmc.h>
25 DECLARE_GLOBAL_DATA_PTR;
29 * Description: Early hardware init.
33 gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
34 /* board id for Linux */
35 gd->bd->bi_arch_number = CONFIG_MACH_TYPE;
37 gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
42 * Routine: set_muxconf_regs
43 * Description: Setting up the configuration Mux registers specific to the
44 * hardware. Many pins need to be moved from protect to primary
47 void set_muxconf_regs(void)
52 #if defined(CONFIG_MMC)
53 int board_mmc_init(bd_t *bis)
55 return omap_mmc_init(0, 0, 0, -1, -1);
59 #ifdef CONFIG_SPL_BUILD
61 * Routine: get_board_mem_timings
62 * Description: If we use SPL then there is no x-loader nor config header
63 * so we have to setup the DDR timings ourself on the first bank. This
64 * provides the timing values back to the function that configures
67 * The Cairo board uses SAMSUNG DDR - K4X51163PG-FGC6
69 void get_board_mem_timings(struct board_sdrc_timings *timings)
71 timings->sharing = SAMSUNG_SHARING;
72 timings->mcfg = SAMSUNG_V_MCFG_165(128 << 20);
73 timings->ctrla = SAMSUNG_V_ACTIMA_165;
74 timings->ctrlb = SAMSUNG_V_ACTIMB_165;
75 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
76 timings->mr = SAMSUNG_V_MR_165;
80 static const struct ns16550_platdata cairo_serial = {
81 .base = OMAP34XX_UART2,
83 .clock = V_NS16550_CLK,
84 .fcr = UART_FCR_DEFVAL,
87 U_BOOT_DEVICE(cairo_uart) = {
92 /* force SPL booting into U-Boot, not Linux */
93 #ifdef CONFIG_SPL_OS_BOOT
94 int spl_start_uboot(void)