2 * Copyright (C) 2008 Prodrive BV <pv@prodrive.nl>
4 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
6 * Parts are shamelessly stolen from various TI sources, original copyright
8 * ---------------------------------------------------------------------------
10 * Copyright (C) 2004 Texas Instruments.
12 * ---------------------------------------------------------------------------
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
26 * ---------------------------------------------------------------------------
31 #include <asm/arch/hardware.h>
32 #include <asm/arch/emac_defs.h>
34 #define MACH_TYPE_DAVINCI_EVM 901
36 DECLARE_GLOBAL_DATA_PTR;
38 extern void timer_init(void);
39 extern int eth_hw_init(void);
42 /* Works on Always On power domain only (no PD argument) */
43 void lpsc_on(unsigned int id)
45 dv_reg_p mdstat, mdctl;
47 if (id >= DAVINCI_LPSC_GEM)
48 return; /* Don't work on DSP Power Domain */
50 mdstat = REG_P(PSC_MDSTAT_BASE + (id * 4));
51 mdctl = REG_P(PSC_MDCTL_BASE + (id * 4));
53 while (REG(PSC_PTSTAT) & 0x01) {; }
55 if ((*mdstat & 0x1f) == 0x03)
56 return; /* Already on and enabled */
60 /* Special treatment for some modules as for sprue14 p.7.4.2 */
61 if ((id == DAVINCI_LPSC_VPSSSLV) ||
62 (id == DAVINCI_LPSC_EMAC) ||
63 (id == DAVINCI_LPSC_EMAC_WRAPPER) ||
64 (id == DAVINCI_LPSC_MDIO) ||
65 (id == DAVINCI_LPSC_USB) ||
66 (id == DAVINCI_LPSC_ATA) ||
67 (id == DAVINCI_LPSC_VLYNQ) ||
68 (id == DAVINCI_LPSC_UHPI) ||
69 (id == DAVINCI_LPSC_DDR_EMIF) ||
70 (id == DAVINCI_LPSC_AEMIF) ||
71 (id == DAVINCI_LPSC_MMC_SD) ||
72 (id == DAVINCI_LPSC_MEMSTICK) ||
73 (id == DAVINCI_LPSC_McBSP) ||
74 (id == DAVINCI_LPSC_GPIO))
77 REG(PSC_PTCMD) = 0x01;
79 while (REG(PSC_PTSTAT) & 0x03) {; }
80 while ((*mdstat & 0x1f) != 0x03) {; } /* Probably an overkill... */
87 if (REG(PSC_PDSTAT1) & 0x1f)
88 return; /* Already on */
90 REG(PSC_GBLCTL) |= 0x01;
91 REG(PSC_PDCTL1) |= 0x01;
92 REG(PSC_PDCTL1) &= ~0x100;
93 REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) |= 0x03;
94 REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) &= 0xfffffeff;
95 REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) |= 0x03;
96 REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) &= 0xfffffeff;
97 REG(PSC_PTCMD) = 0x02;
99 for (i = 0; i < 100; i++) {
100 if (REG(PSC_EPCPR) & 0x02)
104 REG(PSC_CHP_SHRTSW) = 0x01;
105 REG(PSC_PDCTL1) |= 0x100;
106 REG(PSC_EPCCR) = 0x02;
108 for (i = 0; i < 100; i++) {
109 if (!(REG(PSC_PTSTAT) & 0x02))
113 REG(PSC_GBLCTL) &= ~0x1f;
119 /* arch number of the board */
120 gd->bd->bi_arch_number = MACH_TYPE_DAVINCI_EVM;
122 /* address of boot parameters */
123 gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
125 /* Workaround for TMS320DM6446 errata 1.3.22 */
126 REG(PSC_SILVER_BULLET) = 0;
128 /* Power on required peripherals */
129 lpsc_on(DAVINCI_LPSC_EMAC);
130 lpsc_on(DAVINCI_LPSC_EMAC_WRAPPER);
131 lpsc_on(DAVINCI_LPSC_MDIO);
132 lpsc_on(DAVINCI_LPSC_I2C);
133 lpsc_on(DAVINCI_LPSC_UART0);
134 lpsc_on(DAVINCI_LPSC_UART2);
135 lpsc_on(DAVINCI_LPSC_TIMER1);
136 lpsc_on(DAVINCI_LPSC_GPIO);
138 /* Powerup the DSP */
141 /* Bringup UART0 and 2 out of reset */
142 REG(UART0_PWREMU_MGMT) = 0x00006001;
143 REG(UART2_PWREMU_MGMT) = 0x00006001;
145 /* Enable GIO3.3V cells used for EMAC */
146 REG(VDD3P3V_PWDN) = 0;
148 /* Enable UART0 and 2 MUX lines */
152 /* Enable EMAC and AEMIF pins */
153 REG(PINMUX0) = 0x80000c1f;
155 /* Enable I2C pin Mux */
156 REG(PINMUX1) |= (1 << 7);
158 /* Set the Bus Priority Register to appropriate value */
166 int misc_init_r(void)
170 clk = ((REG(PLL2_PLLM) + 1) * 27) / ((REG(PLL2_DIV2) & 0x1f) + 1);
172 printf("ARM Clock : %dMHz\n", ((REG(PLL1_PLLM) + 1) * 27)/2);
173 printf("DDR Clock : %dMHz\n", (clk / 2));
176 printf("ethernet init failed!\n");
178 printf("ETH PHY : %s\n", phy.name);
185 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
186 gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;