3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
5 * SPDX-License-Identifier: GPL-2.0+
10 #if defined(CONFIG_CMD_NAND)
14 struct pdnb3_ndfc_regs {
23 static struct pdnb3_ndfc_regs *pdnb3_ndfc;
25 #define readb(addr) *(volatile u_char *)(addr)
26 #define readl(addr) *(volatile u_long *)(addr)
27 #define writeb(d,addr) *(volatile u_char *)(addr) = (d)
30 * The PDNB3 has a NAND Flash Controller (NDFC) that handles all accesses to
31 * the NAND devices. The NDFC has command, address and data registers that
32 * when accessed will set up the NAND flash pins appropriately. We'll use the
33 * hwcontrol function to save the configuration in a global variable.
34 * We can then use this information in the read and write functions to
35 * determine which NDFC register to access.
37 * There is one NAND devices on the board, a Hynix HY27US08561A (32 MByte).
39 static void pdnb3_nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
41 struct nand_chip *this = mtd->priv;
43 if (ctrl & NAND_CTRL_CHANGE) {
44 if ( ctrl & NAND_CLE )
48 if ( ctrl & NAND_ALE )
52 if ( (ctrl & NAND_NCE) != NAND_NCE)
53 writeb(0x00, &(pdnb3_ndfc->term));
55 if (cmd != NAND_CMD_NONE)
56 writeb(cmd, this->IO_ADDR_W);
60 static u_char pdnb3_nand_read_byte(struct mtd_info *mtd)
62 return readb(&(pdnb3_ndfc->data));
65 static void pdnb3_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
69 for (i = 0; i < len; i++) {
71 writeb(buf[i], &(pdnb3_ndfc->cmd));
73 writeb(buf[i], &(pdnb3_ndfc->addr));
75 writeb(buf[i], &(pdnb3_ndfc->data));
79 static void pdnb3_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
83 for (i = 0; i < len; i++)
84 buf[i] = readb(&(pdnb3_ndfc->data));
87 static int pdnb3_nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len)
91 for (i = 0; i < len; i++)
92 if (buf[i] != readb(&(pdnb3_ndfc->data)))
98 static int pdnb3_nand_dev_ready(struct mtd_info *mtd)
101 * Blocking read to wait for NAND to be ready
103 readb(&(pdnb3_ndfc->wait));
111 int board_nand_init(struct nand_chip *nand)
113 pdnb3_ndfc = (struct pdnb3_ndfc_regs *)CONFIG_SYS_NAND_BASE;
115 nand->ecc.mode = NAND_ECC_SOFT;
117 /* Set address of NAND IO lines (Using Linear Data Access Region) */
118 nand->IO_ADDR_R = (void __iomem *) ((ulong) pdnb3_ndfc + 0x4);
119 nand->IO_ADDR_W = (void __iomem *) ((ulong) pdnb3_ndfc + 0x4);
120 /* Reference hardware control function */
121 nand->cmd_ctrl = pdnb3_nand_hwcontrol;
122 nand->read_byte = pdnb3_nand_read_byte;
123 nand->write_buf = pdnb3_nand_write_buf;
124 nand->read_buf = pdnb3_nand_read_buf;
125 nand->verify_buf = pdnb3_nand_verify_buf;
126 nand->dev_ready = pdnb3_nand_dev_ready;