2 * Copyright 2004 Freescale Semiconductor.
3 * Copyright (C) 2002,2003, Motorola Inc.
4 * Xianghua Xiao <X.Xiao@motorola.com>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include <ppc_asm.tmpl>
27 #include <asm/cache.h>
34 * TLB0 and TLB1 Entries
36 * Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR.
37 * However, CCSRBAR is then relocated to CFG_CCSRBAR right after
38 * these TLB entries are established.
40 * The TLB entries for DDR are dynamically setup in spd_sdram()
41 * and use TLB1 Entries 8 through 15 as needed according to the
44 * MAS0: tlbsel, esel, nv
45 * MAS1: valid, iprot, tid, ts, tsize
46 * MAS2: epn, x0, x1, w, i, m, g, e
47 * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr
60 .section .bootpg, "ax"
66 * Number of TLB0 and TLB1 entries in the following table
70 #if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
72 * TLB0 4K Non-cacheable, guarded
73 * 0xff700000 4K Initial CCSRBAR mapping
75 * This ends up at a TLB0 Index==0 entry, and must not collide
76 * with other TLB0 Entries.
78 .long FSL_BOOKE_MAS0(0, 0, 0)
79 .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
80 .long FSL_BOOKE_MAS2(CFG_CCSRBAR_DEFAULT, (MAS2_I|MAS2_G))
81 .long FSL_BOOKE_MAS3(CFG_CCSRBAR_DEFAULT, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
83 #error("Update the number of table entries in tlb1_entry")
87 * TLB0 16K Cacheable, non-guarded
88 * 0xd001_0000 16K Temporary Global data for initialization
90 * Use four 4K TLB0 entries. These entries must be cacheable
91 * as they provide the bootstrap memory before the memory
92 * controler and real memory have been configured.
94 * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c,
95 * and must not collide with other TLB0 entries.
97 .long FSL_BOOKE_MAS0(0, 0, 0)
98 .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
99 .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR, 0)
100 .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
102 .long FSL_BOOKE_MAS0(0, 0, 0)
103 .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
104 .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 4 * 1024, 0)
105 .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 4 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
107 .long FSL_BOOKE_MAS0(0, 0, 0)
108 .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
109 .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 8 * 1024, 0)
110 .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 8 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
112 .long FSL_BOOKE_MAS0(0, 0, 0)
113 .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
114 .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 12 * 1024, 0)
115 .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 12 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
119 * TLB 0: 64M Non-cacheable, guarded
120 * 0xfc000000 64M FLASH (8,16,32 or 64 MB)
121 * Out of reset this entry is only 4K.
123 .long FSL_BOOKE_MAS0(1, 0, 0)
124 .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
125 .long FSL_BOOKE_MAS2(0xfc000000, (MAS2_I|MAS2_G))
126 .long FSL_BOOKE_MAS3(0xfc000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
129 * TLB 1: 256M Non-cacheable, guarded
130 * 0x80000000 256M PCI1 MEM First half
132 .long FSL_BOOKE_MAS0(1, 1, 0)
133 .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
134 .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_BASE, (MAS2_I|MAS2_G))
135 .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
138 * TLB 2: 256M Non-cacheable, guarded
139 * 0x90000000 256M PCI1 MEM Second half
141 .long FSL_BOOKE_MAS0(1, 2, 0)
142 .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
143 .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_BASE + 0x10000000, (MAS2_I|MAS2_G))
144 .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_BASE + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
147 * TLB 3: 256M Non-cacheable, guarded
148 * 0xc0000000 256M Rapid IO MEM First half
150 .long FSL_BOOKE_MAS0(1, 3, 0)
151 .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
152 .long FSL_BOOKE_MAS2(CFG_RIO_MEM_BASE, (MAS2_I|MAS2_G))
153 .long FSL_BOOKE_MAS3(CFG_RIO_MEM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
156 * TLB 4: 256M Non-cacheable, guarded
157 * 0xd0000000 256M Rapid IO MEM Second half
159 .long FSL_BOOKE_MAS0(1, 4, 0)
160 .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
161 .long FSL_BOOKE_MAS2(CFG_RIO_MEM_BASE + 0x10000000, (MAS2_I|MAS2_G))
162 .long FSL_BOOKE_MAS3(CFG_RIO_MEM_BASE + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
165 * TLB 5: 64M Non-cacheable, guarded
166 * 0xe000_0000 1M CCSRBAR
167 * 0xe200_0000 16M PCI1 IO
169 .long FSL_BOOKE_MAS0(1, 5, 0)
170 .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
171 .long FSL_BOOKE_MAS2(CFG_CCSRBAR, (MAS2_I|MAS2_G))
172 .long FSL_BOOKE_MAS3(CFG_CCSRBAR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
175 * TLB 6: 64M Cacheable, non-guarded
176 * 0xf000_0000 64M LBC SDRAM
178 .long FSL_BOOKE_MAS0(1, 6, 0)
179 .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
180 .long FSL_BOOKE_MAS2(CFG_LBC_SDRAM_BASE, 0)
181 .long FSL_BOOKE_MAS3(CFG_LBC_SDRAM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
183 #if !defined(CONFIG_SPD_EEPROM)
186 * 0x00000000 256M DDR System memory
187 * Without SPD EEPROM configured DDR, this must be setup manually.
188 * Make sure the TLB count at the top of this table is correct.
189 * Likely it needs to be increased by two for these entries.
192 .long FSL_BOOKE_MAS0(1, 7, 0)
193 .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
194 .long FSL_BOOKE_MAS2(CFG_DDR_SDRAM_BASE, 0)
195 .long FSL_BOOKE_MAS3(CFG_DDR_SDRAM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
201 * LAW(Local Access Window) configuration:
203 * 0x0000_0000 0x7fff_ffff DDR 2G
204 * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
205 * 0xc000_0000 0xdfff_ffff RapidIO 512M
206 * 0xe000_0000 0xe000_ffff CCSR 1M
207 * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M
208 * 0xf000_0000 0xf7ff_ffff SDRAM 128M
209 * 0xf800_0000 0xf80f_ffff BCSR 1M
210 * 0xfc00_0000 0xffff_ffff FLASH (boot bank) 64M
213 * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
214 * If flash is 8M at default position (last 8M), no LAW needed.
217 #if !defined(CONFIG_SPD_EEPROM)
218 #define LAWBAR0 ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff)
219 #define LAWAR0 (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_256M))
222 #define LAWAR0 ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN)
225 #define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff)
226 #define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_512M))
229 * This is not so much the SDRAM map as it is the whole localbus map.
231 #define LAWBAR2 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff)
232 #define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M))
234 #define LAWBAR3 ((CFG_PCI1_IO_BASE>>12) & 0xfffff)
235 #define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_16M))
238 * Rapid IO at 0xc000_0000 for 512 M
240 #define LAWBAR4 ((CFG_RIO_MEM_BASE>>12) & 0xfffff)
241 #define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M))
244 .section .bootpg, "ax"
249 .long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2,LAWBAR3,LAWAR3