2 * Copyright 2004 Freescale Semiconductor.
3 * (C) Copyright 2002,2003, Motorola Inc.
4 * Xianghua Xiao, (X.Xiao@motorola.com)
6 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 #include <asm/processor.h>
32 #include <asm/immap_85xx.h>
33 #include <asm/fsl_ddr_sdram.h>
34 #include <spd_sdram.h>
36 #if defined(CONFIG_DDR_ECC)
37 extern void ddr_enable_ecc(unsigned int dram_size);
40 void local_bus_init(void);
41 void sdram_init(void);
42 long int fixed_sdram(void);
45 int board_early_init_f (void)
47 #if defined(CONFIG_PCI)
48 volatile ccsr_pcix_t *pci = (void *)(CFG_MPC85xx_PCIX_ADDR);
50 pci->peer &= 0xffffffdf; /* disable master abort */
58 puts("Board: MicroSys PM854\n");
61 printf(" PCI1: 32 bit, %d MHz (compiled)\n",
62 CONFIG_SYS_CLK_FREQ / 1000000);
64 printf(" PCI1: disabled\n");
68 * Initialize local bus.
77 initdram(int board_type)
81 puts("Initializing\n");
83 #if defined(CONFIG_DDR_DLL)
85 volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
91 * Work around to stabilize DDR DLL
93 gur->ddrdllcr = 0x81000000;
94 asm("sync;isync;msync");
96 while (gur->ddrdllcr != 0x81000100)
98 gur->devdisr = gur->devdisr | 0x00010000;
99 asm("sync;isync;msync");
102 gur->devdisr = gur->devdisr & 0xfff7ffff;
103 asm("sync;isync;msync");
109 #if defined(CONFIG_SPD_EEPROM)
110 dram_size = fsl_ddr_sdram();
111 dram_size = setup_ddr_tlbs(dram_size / 0x100000);
112 dram_size *= 0x100000;
114 dram_size = fixed_sdram ();
117 #if defined(CONFIG_DDR_ECC)
119 * Initialize and enable DDR ECC.
121 ddr_enable_ecc(dram_size);
129 * Initialize Local Bus
135 volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
136 volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
144 * Fix Local Bus clock glitch when DLL is enabled.
146 * If localbus freq is < 66Mhz, DLL bypass mode must be used.
147 * If localbus freq is > 133Mhz, DLL can be safely enabled.
148 * Between 66 and 133, the DLL is enabled with an override workaround.
151 get_sys_info(&sysinfo);
152 clkdiv = lbc->lcrr & 0x0f;
153 lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
156 lbc->lcrr = CFG_LBC_LCRR | 0x80000000; /* DLL Bypass */
158 } else if (lbc_hz >= 133) {
159 lbc->lcrr = CFG_LBC_LCRR & (~0x80000000); /* DLL Enabled */
163 * On REV1 boards, need to change CLKDIV before enable DLL.
164 * Default CLKDIV is 8, change it to 4 temporarily.
166 uint pvr = get_pvr();
167 uint temp_lbcdll = 0;
169 if (pvr == PVR_85xx_REV1) {
170 /* FIXME: Justify the high bit here. */
171 lbc->lcrr = 0x10000004;
174 lbc->lcrr = CFG_LBC_LCRR & (~0x80000000); /* DLL Enabled */
178 * Sample LBC DLL ctrl reg, upshift it to set the
181 temp_lbcdll = gur->lbcdllcr;
182 gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000);
183 asm("sync;isync;msync");
188 #if defined(CFG_DRAM_TEST)
191 uint *pstart = (uint *) CFG_MEMTEST_START;
192 uint *pend = (uint *) CFG_MEMTEST_END;
195 printf("SDRAM test phase 1:\n");
196 for (p = pstart; p < pend; p++)
199 for (p = pstart; p < pend; p++) {
200 if (*p != 0xaaaaaaaa) {
201 printf ("SDRAM test fails at: %08x\n", (uint) p);
206 printf("SDRAM test phase 2:\n");
207 for (p = pstart; p < pend; p++)
210 for (p = pstart; p < pend; p++) {
211 if (*p != 0x55555555) {
212 printf ("SDRAM test fails at: %08x\n", (uint) p);
217 printf("SDRAM test passed.\n");
223 #if !defined(CONFIG_SPD_EEPROM)
224 /*************************************************************************
225 * fixed sdram init -- doesn't use serial presence detect.
226 ************************************************************************/
227 long int fixed_sdram (void)
230 volatile ccsr_ddr_t *ddr= (void *)(CFG_MPC85xx_DDR_ADDR);
232 ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
233 ddr->cs0_config = CFG_DDR_CS0_CONFIG;
234 ddr->timing_cfg_1 = CFG_DDR_TIMING_1;
235 ddr->timing_cfg_2 = CFG_DDR_TIMING_2;
236 ddr->sdram_mode = CFG_DDR_MODE;
237 ddr->sdram_interval = CFG_DDR_INTERVAL;
238 #if defined (CONFIG_DDR_ECC)
239 ddr->err_disable = 0x0000000D;
240 ddr->err_sbe = 0x00ff0000;
242 asm("sync;isync;msync");
244 #if defined (CONFIG_DDR_ECC)
245 /* Enable ECC checking */
246 ddr->sdram_cfg = (CFG_DDR_CONTROL | 0x20000000);
248 ddr->sdram_cfg = CFG_DDR_CONTROL;
250 asm("sync; isync; msync");
253 return CFG_SDRAM_SIZE * 1024 * 1024;
255 #endif /* !defined(CONFIG_SPD_EEPROM) */
258 #if defined(CONFIG_PCI)
260 * Initialize PCI Devices, report devices found.
263 #ifndef CONFIG_PCI_PNP
264 static struct pci_config_table pci_pm854_config_table[] = {
265 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
266 PCI_IDSEL_NUMBER, PCI_ANY_ID,
267 pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
269 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER
276 static struct pci_controller hose = {
277 #ifndef CONFIG_PCI_PNP
278 config_table: pci_pm854_config_table,
282 #endif /* CONFIG_PCI */
289 pci_mpc85xx_init(&hose);
290 #endif /* CONFIG_PCI */