2 * Copyright 2004 Freescale Semiconductor.
3 * (C) Copyright 2002,2003, Motorola Inc.
4 * Xianghua Xiao, (X.Xiao@motorola.com)
6 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 #include <asm/processor.h>
33 #include <asm/immap_85xx.h>
34 #include <asm/fsl_ddr_sdram.h>
35 #include <spd_sdram.h>
37 #if defined(CONFIG_DDR_ECC)
38 extern void ddr_enable_ecc(unsigned int dram_size);
41 void local_bus_init(void);
42 void sdram_init(void);
43 long int fixed_sdram(void);
46 int board_early_init_f (void)
48 #if defined(CONFIG_PCI)
49 volatile ccsr_pcix_t *pci = (void *)(CFG_MPC85xx_PCIX_ADDR);
51 pci->peer &= 0xffffffdf; /* disable master abort */
59 puts("Board: MicroSys PM854\n");
62 printf(" PCI1: 32 bit, %d MHz (compiled)\n",
63 CONFIG_SYS_CLK_FREQ / 1000000);
65 printf(" PCI1: disabled\n");
69 * Initialize local bus.
78 initdram(int board_type)
82 puts("Initializing\n");
84 #if defined(CONFIG_DDR_DLL)
86 volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
92 * Work around to stabilize DDR DLL
94 gur->ddrdllcr = 0x81000000;
95 asm("sync;isync;msync");
97 while (gur->ddrdllcr != 0x81000100)
99 gur->devdisr = gur->devdisr | 0x00010000;
100 asm("sync;isync;msync");
103 gur->devdisr = gur->devdisr & 0xfff7ffff;
104 asm("sync;isync;msync");
110 #if defined(CONFIG_SPD_EEPROM)
111 dram_size = fsl_ddr_sdram();
112 dram_size = setup_ddr_tlbs(dram_size / 0x100000);
113 dram_size *= 0x100000;
115 dram_size = fixed_sdram ();
118 #if defined(CONFIG_DDR_ECC)
120 * Initialize and enable DDR ECC.
122 ddr_enable_ecc(dram_size);
130 * Initialize Local Bus
136 volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
137 volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
145 * Fix Local Bus clock glitch when DLL is enabled.
147 * If localbus freq is < 66Mhz, DLL bypass mode must be used.
148 * If localbus freq is > 133Mhz, DLL can be safely enabled.
149 * Between 66 and 133, the DLL is enabled with an override workaround.
152 get_sys_info(&sysinfo);
153 clkdiv = lbc->lcrr & 0x0f;
154 lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
157 lbc->lcrr = CFG_LBC_LCRR | 0x80000000; /* DLL Bypass */
159 } else if (lbc_hz >= 133) {
160 lbc->lcrr = CFG_LBC_LCRR & (~0x80000000); /* DLL Enabled */
164 * On REV1 boards, need to change CLKDIV before enable DLL.
165 * Default CLKDIV is 8, change it to 4 temporarily.
167 uint pvr = get_pvr();
168 uint temp_lbcdll = 0;
170 if (pvr == PVR_85xx_REV1) {
171 /* FIXME: Justify the high bit here. */
172 lbc->lcrr = 0x10000004;
175 lbc->lcrr = CFG_LBC_LCRR & (~0x80000000); /* DLL Enabled */
179 * Sample LBC DLL ctrl reg, upshift it to set the
182 temp_lbcdll = gur->lbcdllcr;
183 gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000);
184 asm("sync;isync;msync");
189 #if defined(CFG_DRAM_TEST)
192 uint *pstart = (uint *) CFG_MEMTEST_START;
193 uint *pend = (uint *) CFG_MEMTEST_END;
196 printf("SDRAM test phase 1:\n");
197 for (p = pstart; p < pend; p++)
200 for (p = pstart; p < pend; p++) {
201 if (*p != 0xaaaaaaaa) {
202 printf ("SDRAM test fails at: %08x\n", (uint) p);
207 printf("SDRAM test phase 2:\n");
208 for (p = pstart; p < pend; p++)
211 for (p = pstart; p < pend; p++) {
212 if (*p != 0x55555555) {
213 printf ("SDRAM test fails at: %08x\n", (uint) p);
218 printf("SDRAM test passed.\n");
224 #if !defined(CONFIG_SPD_EEPROM)
225 /*************************************************************************
226 * fixed sdram init -- doesn't use serial presence detect.
227 ************************************************************************/
228 long int fixed_sdram (void)
231 volatile ccsr_ddr_t *ddr= (void *)(CFG_MPC85xx_DDR_ADDR);
233 ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
234 ddr->cs0_config = CFG_DDR_CS0_CONFIG;
235 ddr->timing_cfg_1 = CFG_DDR_TIMING_1;
236 ddr->timing_cfg_2 = CFG_DDR_TIMING_2;
237 ddr->sdram_mode = CFG_DDR_MODE;
238 ddr->sdram_interval = CFG_DDR_INTERVAL;
239 #if defined (CONFIG_DDR_ECC)
240 ddr->err_disable = 0x0000000D;
241 ddr->err_sbe = 0x00ff0000;
243 asm("sync;isync;msync");
245 #if defined (CONFIG_DDR_ECC)
246 /* Enable ECC checking */
247 ddr->sdram_cfg = (CFG_DDR_CONTROL | 0x20000000);
249 ddr->sdram_cfg = CFG_DDR_CONTROL;
251 asm("sync; isync; msync");
254 return CFG_SDRAM_SIZE * 1024 * 1024;
256 #endif /* !defined(CONFIG_SPD_EEPROM) */
259 #if defined(CONFIG_PCI)
261 * Initialize PCI Devices, report devices found.
264 #ifndef CONFIG_PCI_PNP
265 static struct pci_config_table pci_pm854_config_table[] = {
266 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
267 PCI_IDSEL_NUMBER, PCI_ANY_ID,
268 pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
270 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER
277 static struct pci_controller hose = {
278 #ifndef CONFIG_PCI_PNP
279 config_table: pci_pm854_config_table,
283 #endif /* CONFIG_PCI */
290 pci_mpc85xx_init(&hose);
291 #endif /* CONFIG_PCI */
294 int board_eth_init(bd_t *bis)
296 return pci_eth_init(bis);