1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2016 Rockchip Electronics Co., Ltd
4 * (C) Copyright 2020 Peter Robinson <pbrobinson at gmail.com>
11 #include <asm/arch-rockchip/clock.h>
12 #include <asm/arch-rockchip/grf_rk3399.h>
13 #include <asm/arch-rockchip/hardware.h>
14 #include <asm/arch-rockchip/misc.h>
15 #include <power/regulator.h>
17 #define GRF_IO_VSEL_BT565_SHIFT 0
18 #define PMUGRF_CON0_VSEL_SHIFT 8
20 #ifndef CONFIG_SPL_BUILD
21 int board_early_init_f(void)
23 struct udevice *regulator;
26 ret = regulator_get_by_platname("vcc5v0_usb", ®ulator);
28 pr_debug("%s vcc5v0_usb init fail! ret %d\n", __func__, ret);
32 ret = regulator_set_enable(regulator, true);
34 pr_debug("%s vcc5v0-host-en-gpio set fail! ret %d\n", __func__, ret);
41 #ifdef CONFIG_MISC_INIT_R
42 static void setup_iodomain(void)
44 struct rk3399_grf_regs *grf =
45 syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
46 struct rk3399_pmugrf_regs *pmugrf =
47 syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
49 /* BT565 is in 1.8v domain */
50 rk_setreg(&grf->io_vsel, 1 << GRF_IO_VSEL_BT565_SHIFT);
52 /* Set GPIO1 1.8v/3.0v source select to PMU1830_VOL */
53 rk_setreg(&pmugrf->soc_con0, 1 << PMUGRF_CON0_VSEL_SHIFT);
58 const u32 cpuid_offset = 0x7;
59 const u32 cpuid_length = 0x10;
60 u8 cpuid[cpuid_length];
65 ret = rockchip_cpuid_from_efuse(cpuid_offset, cpuid_length, cpuid);
69 ret = rockchip_cpuid_set(cpuid, cpuid_length);