board/phytium/durian/durian.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2019
   4  * shuyiqi <shuyiqi@phytium.com.cn>
   5  * liuhao  <liuhao@phytium.com.cn>
   6  */
   7
   8 #include <common.h>
   9 #include <cpu_func.h>
  10 #include <asm/armv8/mmu.h>
  11 #include <asm/system.h>
  12 #include <asm/io.h>
  13 #include <linux/arm-smccc.h>
  14 #include <linux/kernel.h>
  15 #include <scsi.h>
  16 #include "cpu.h"
  17
  18 DECLARE_GLOBAL_DATA_PTR;
  19
  20 int dram_init(void)
  21 {
  22         gd->mem_clk = 0;
  23         gd->ram_size = PHYS_SDRAM_1_SIZE;
  24         return 0;
  25 }
  26
  27 int dram_init_banksize(void)
  28 {
  29         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
  30         gd->bd->bi_dram[0].size =  PHYS_SDRAM_1_SIZE;
  31
  32         return 0;
  33 }
  34
  35 int board_init(void)
  36 {
  37         return 0;
  38 }
  39
  40 void reset_cpu(ulong addr)
  41 {
  42         struct arm_smccc_res res;
  43
  44         arm_smccc_smc(0x84000009, 0, 0, 0, 0, 0, 0, 0, &res);
  45         debug("reset cpu error, %lx\n", res.a0);
  46 }
  47
  48 static struct mm_region durian_mem_map[] = {
  49         {
  50                 .virt = 0x0UL,
  51                 .phys = 0x0UL,
  52                 .size = 0x80000000UL,
  53                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  54                                  PTE_BLOCK_NON_SHARE |
  55                                  PTE_BLOCK_PXN |
  56                                  PTE_BLOCK_UXN
  57         },
  58         {
  59                 .virt = (u64)PHYS_SDRAM_1,
  60                 .phys = (u64)PHYS_SDRAM_1,
  61                 .size = (u64)PHYS_SDRAM_1_SIZE,
  62                 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  63                                  PTE_BLOCK_NS |
  64                                  PTE_BLOCK_INNER_SHARE
  65         },
  66         {
  67                 0,
  68         }
  69 };
  70
  71 struct mm_region *mem_map = durian_mem_map;
  72
  73 int print_cpuinfo(void)
  74 {
  75         printf("CPU: Phytium ft2004 %ld MHz\n", gd->cpu_clk);
  76         return 0;
  77 }
  78
  79 int __asm_flush_l3_dcache(void)
  80 {
  81         int i, pstate;
  82
  83         for (i = 0; i < HNF_COUNT; i++)
  84                 writeq(HNF_PSTATE_SFONLY, HNF_PSTATE_REQ + i * HNF_STRIDE);
  85         for (i = 0; i < HNF_COUNT; i++) {
  86                 do {
  87                         pstate = readq(HNF_PSTATE_STAT + i * HNF_STRIDE);
  88                 } while ((pstate & 0xf) != (HNF_PSTATE_SFONLY << 2));
  89         }
  90
  91         for (i = 0; i < HNF_COUNT; i++)
  92                 writeq(HNF_PSTATE_FULL, HNF_PSTATE_REQ + i * HNF_STRIDE);
  93
  94         return 0;
  95 }
  96
  97 int last_stage_init(void)
  98 {
  99         int ret;
 100
 101         /* pci e */
 102         pci_init();
 103         /* scsi scan */
 104         ret = scsi_scan(true);
 105         if (ret) {
 106                 printf("scsi scan failed\n");
 107                 return CMD_RET_FAILURE;
 108         }
 109         return ret;
 110 }
 111