2 * (C) Copyright 2009, 2010 Wolfgang Denk <wd@denx.de>
4 * (C) Copyright 2009-2010
5 * Michael Weiß, ifm ecomatic gmbh, michael.weiss@ifm.com
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 #include <asm/bitops.h>
31 #include <asm/processor.h>
32 #include <asm/mpc512x.h>
33 #include <fdt_support.h>
35 #ifdef CONFIG_MISC_INIT_R
39 #include <jffs2/load_kernel.h>
42 DECLARE_GLOBAL_DATA_PTR;
44 extern flash_info_t flash_info[];
45 ulong flash_get_size (phys_addr_t base, int banknum);
48 #define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN | \
49 CLOCK_SCCR1_LPC_EN | \
50 CLOCK_SCCR1_NFC_EN | \
51 CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) | \
52 CLOCK_SCCR1_PSCFIFO_EN | \
53 CLOCK_SCCR1_DDR_EN | \
54 CLOCK_SCCR1_FEC_EN | \
57 #define SCCR2_CLOCKS_EN (CLOCK_SCCR2_MEM_EN | \
58 CLOCK_SCCR2_SPDIF_EN | \
59 CLOCK_SCCR2_DIU_EN | \
62 int board_early_init_f(void)
64 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
67 * Initialize Local Window for FLASH-Bank1 access (CS1)
69 out_be32(&im->sysconf.lpcs1aw,
70 CSAW_START(CONFIG_SYS_FLASH1_BASE) |
71 CSAW_STOP(CONFIG_SYS_FLASH1_BASE, CONFIG_SYS_FLASH_SIZE)
73 out_be32(&im->lpc.cs_cfg[1], CONFIG_SYS_CS1_CFG);
76 * Local Window for MRAM access (CS2)
78 out_be32(&im->sysconf.lpcs2aw,
79 CSAW_START(CONFIG_SYS_MRAM_BASE) |
80 CSAW_STOP(CONFIG_SYS_MRAM_BASE, CONFIG_SYS_MRAM_SIZE)
82 out_be32(&im->lpc.cs_cfg[2], CONFIG_SYS_CS2_CFG);
84 sync_law(&im->sysconf.lpcs2aw);
87 * Configure Flash Speed
89 out_be32(&im->lpc.cs_cfg[0], CONFIG_SYS_CS0_CFG);
90 out_be32(&im->lpc.altr, CONFIG_SYS_CS_ALETIMING);
95 out_be32(&im->clk.sccr[0], SCCR1_CLOCKS_EN);
96 out_be32(&im->clk.sccr[1], SCCR2_CLOCKS_EN);
97 #if defined(CONFIG_IIM) || defined(CONFIG_CMD_FUSE)
98 setbits_be32(&im->clk.sccr[1], CLOCK_SCCR2_IIM_EN);
104 sdram_conf_t mddrc_config[] = {
106 (512 << 20), /* 512 MB RAM configuration */
108 CONFIG_SYS_MDDRC_SYS_CFG,
109 CONFIG_SYS_MDDRC_TIME_CFG0,
110 CONFIG_SYS_MDDRC_TIME_CFG1,
111 CONFIG_SYS_MDDRC_TIME_CFG2
115 (128 << 20), /* 128 MB RAM configuration */
117 CONFIG_SYS_MDDRC_SYS_CFG_ALT1,
118 CONFIG_SYS_MDDRC_TIME_CFG0_ALT1,
119 CONFIG_SYS_MDDRC_TIME_CFG1_ALT1,
120 CONFIG_SYS_MDDRC_TIME_CFG2_ALT1
125 phys_size_t initdram (int board_type)
129 u32 pdm360ng_init_seq[] = {
130 CONFIG_SYS_DDRCMD_NOP,
131 CONFIG_SYS_DDRCMD_NOP,
132 CONFIG_SYS_DDRCMD_NOP,
133 CONFIG_SYS_DDRCMD_NOP,
134 CONFIG_SYS_DDRCMD_NOP,
135 CONFIG_SYS_DDRCMD_NOP,
136 CONFIG_SYS_DDRCMD_NOP,
137 CONFIG_SYS_DDRCMD_NOP,
138 CONFIG_SYS_DDRCMD_NOP,
139 CONFIG_SYS_DDRCMD_NOP,
140 CONFIG_SYS_DDRCMD_PCHG_ALL,
141 CONFIG_SYS_DDRCMD_NOP,
142 CONFIG_SYS_DDRCMD_RFSH,
143 CONFIG_SYS_DDRCMD_NOP,
144 CONFIG_SYS_DDRCMD_RFSH,
145 CONFIG_SYS_DDRCMD_NOP,
146 CONFIG_SYS_MICRON_INIT_DEV_OP,
147 CONFIG_SYS_DDRCMD_NOP,
148 CONFIG_SYS_DDRCMD_EM2,
149 CONFIG_SYS_DDRCMD_NOP,
150 CONFIG_SYS_DDRCMD_PCHG_ALL,
151 CONFIG_SYS_DDRCMD_EM2,
152 CONFIG_SYS_DDRCMD_EM3,
153 CONFIG_SYS_DDRCMD_EN_DLL,
154 CONFIG_SYS_DDRCMD_RES_DLL,
155 CONFIG_SYS_DDRCMD_PCHG_ALL,
156 CONFIG_SYS_DDRCMD_RFSH,
157 CONFIG_SYS_DDRCMD_RFSH,
158 CONFIG_SYS_MICRON_INIT_DEV_OP,
159 CONFIG_SYS_DDRCMD_OCD_DEFAULT,
160 CONFIG_SYS_DDRCMD_OCD_EXIT,
161 CONFIG_SYS_DDRCMD_PCHG_ALL,
162 CONFIG_SYS_DDRCMD_NOP
165 for (i = 0; i < ARRAY_SIZE(mddrc_config); i++) {
166 msize = fixed_sdram(&mddrc_config[i].cfg, pdm360ng_init_seq,
167 ARRAY_SIZE(pdm360ng_init_seq));
168 if (msize == mddrc_config[i].size)
175 static int set_lcd_brightness(char *);
177 int misc_init_r(void)
179 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
182 * Re-configure flash setup using auto-detected info
184 if (flash_info[1].size > 0) {
185 out_be32(&im->sysconf.lpcs1aw,
186 CSAW_START(gd->bd->bi_flashstart + flash_info[1].size) |
187 CSAW_STOP(gd->bd->bi_flashstart + flash_info[1].size,
188 flash_info[1].size));
189 sync_law(&im->sysconf.lpcs1aw);
191 * Re-check to get correct base address
193 flash_get_size (gd->bd->bi_flashstart + flash_info[1].size, 1);
196 out_be32(&im->sysconf.lpcs1aw, 0x01000100);
197 sync_law(&im->sysconf.lpcs1aw);
200 out_be32(&im->sysconf.lpcs0aw,
201 CSAW_START(gd->bd->bi_flashstart) |
202 CSAW_STOP(gd->bd->bi_flashstart, flash_info[0].size));
203 sync_law(&im->sysconf.lpcs0aw);
206 * Re-check to get correct base address
208 flash_get_size (gd->bd->bi_flashstart, 0);
211 * Re-do flash protection upon new addresses
213 flash_protect (FLAG_PROTECT_CLEAR,
214 gd->bd->bi_flashstart, 0xffffffff,
217 /* Monitor protection ON by default */
218 flash_protect (FLAG_PROTECT_SET,
219 CONFIG_SYS_MONITOR_BASE,
220 CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN - 1,
223 /* Environment protection ON by default */
224 flash_protect (FLAG_PROTECT_SET,
226 CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
229 #ifdef CONFIG_ENV_ADDR_REDUND
230 /* Redundant environment protection ON by default */
231 flash_protect (FLAG_PROTECT_SET,
232 CONFIG_ENV_ADDR_REDUND,
233 CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1,
237 #ifdef CONFIG_FSL_DIU_FB
238 set_lcd_brightness(0);
239 /* Switch LCD-Backlight and LVDS-Interface on */
240 setbits_be32(&im->gpio.gpdir, 0x01040000);
241 clrsetbits_be32(&im->gpio.gpdat, 0x01000000, 0x00040000);
244 #if defined(CONFIG_HARD_I2C)
245 if (!getenv("ethaddr")) {
247 uchar ifm_oui[3] = { 0, 2, 1, };
250 /* I2C-0 for on-board eeprom */
251 i2c_set_bus_num(CONFIG_SYS_I2C_EEPROM_BUS_NUM);
253 /* Read ethaddr from EEPROM */
254 ret = i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR,
255 CONFIG_SYS_I2C_EEPROM_MAC_OFFSET, 1, buf, 6);
257 printf("Error: Unable to read MAC from I2C"
258 " EEPROM at address %02X:%02X\n",
259 CONFIG_SYS_I2C_EEPROM_ADDR,
260 CONFIG_SYS_I2C_EEPROM_MAC_OFFSET);
265 if (memcmp(buf, ifm_oui, sizeof(ifm_oui))) {
266 printf("Illegal MAC address in EEPROM: %pM\n", buf);
270 eth_setenv_enetaddr("ethaddr", buf);
272 #endif /* defined(CONFIG_HARD_I2C) */
277 static iopin_t ioregs_init[] = {
280 offsetof(struct ioctrl512x, io_control_pata_ce1), 1, 0,
281 IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(1) |
282 IO_PIN_PUE(1) | IO_PIN_ST(0) | IO_PIN_DS(3)
286 offsetof(struct ioctrl512x, io_control_pata_ce2), 1, 0,
287 IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
288 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
292 offsetof(struct ioctrl512x, io_control_pata_isolate), 1, 0,
293 IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
294 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
298 offsetof(struct ioctrl512x, io_control_pata_iochrdy), 1, 0,
299 IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
300 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
302 /* FUNC2=DIU_LD22 Sets Next 2 to DIU_LD pads */
303 /* DIU_LD22-DIU_LD23 */
305 offsetof(struct ioctrl512x, io_control_pci_ad31), 2, 0,
306 IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
307 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(1)
309 /* FUNC2=USB1_DATA7 Sets Next 12 to USB1 pads */
310 /* USB1_DATA7-USB1_DATA0, USB1_STOP, USB1_NEXT, USB1_CLK, USB1_DIR */
312 offsetof(struct ioctrl512x, io_control_pci_ad29), 12, 0,
313 IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
314 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(1)
316 /* FUNC1=VIU_DATA0 Sets Next 3 to VIU_DATA pads */
317 /* VIU_DATA0-VIU_DATA2 */
319 offsetof(struct ioctrl512x, io_control_pci_ad17), 3, 0,
320 IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
321 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(1)
323 /* FUNC2=FEC_TXD_0 */
325 offsetof(struct ioctrl512x, io_control_pci_ad14), 1, 0,
326 IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
327 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(1)
329 /* FUNC1=VIU_DATA3 Sets Next 2 to VIU_DATA pads */
330 /* VIU_DATA3, VIU_DATA4 */
332 offsetof(struct ioctrl512x, io_control_pci_ad13), 2, 0,
333 IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
334 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(1)
336 /* FUNC2=FEC_RXD_1 Sets Next 12 to FEC pads */
337 /* FEC_RXD_1, FEC_RXD_0, FEC_RX_CLK, FEC_TX_CLK, FEC_RX_ER, FEC_RX_DV */
338 /* FEC_TX_EN, FEC_TX_ER, FEC_CRS, FEC_MDC, FEC_MDIO, FEC_COL */
340 offsetof(struct ioctrl512x, io_control_pci_ad11), 12, 0,
341 IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
342 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(1)
344 /* FUNC2=DIU_LD03 Sets Next 25 to DIU pads */
345 /* DIU_LD00-DIU_LD21 */
347 offsetof(struct ioctrl512x, io_control_pci_cbe0), 22, 0,
348 IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
349 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(1)
351 /* FUNC2=DIU_CLK Sets Next 3 to DIU pads */
352 /* DIU_CLK, DIU_VSYNC, DIU_HSYNC */
354 offsetof(struct ioctrl512x, io_control_spdif_txclk), 3, 0,
355 IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
356 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
360 offsetof(struct ioctrl512x, io_control_irq1), 1, 0,
361 IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
362 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
364 /* Sets lowest slew on 2 CAN_TX Pins*/
366 offsetof(struct ioctrl512x, io_control_can1_tx), 2, 0,
367 IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
368 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
370 /* FUNC3=CAN4_TX Sets Next 2 to CAN4 pads */
371 /* CAN4_TX, CAN4_RX */
373 offsetof(struct ioctrl512x, io_control_j1850_tx), 2, 0,
374 IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
375 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
377 /* FUNC3=GPIO8 Sets Next 2 to GPIO pads */
380 offsetof(struct ioctrl512x, io_control_psc0_0), 2, 0,
381 IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
382 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
384 /* FUNC1=FEC_TXD_1 Sets Next 3 to FEC pads */
385 /* FEC_TXD_1, FEC_TXD_2, FEC_TXD_3 */
387 offsetof(struct ioctrl512x, io_control_psc0_4), 3, 0,
388 IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
389 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
391 /* FUNC1=FEC_RXD_3 Sets Next 2 to FEC pads */
392 /* FEC_RXD_3, FEC_RXD_2 */
394 offsetof(struct ioctrl512x, io_control_psc1_4), 2, 0,
395 IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
396 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
400 offsetof(struct ioctrl512x, io_control_psc2_1), 1, 0,
401 IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
402 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
404 /* FUNC3=GPIO2/GPT2 Sets Next 3 to GPIO pads */
405 /* GPIO2, GPIO20, GPIO21 */
407 offsetof(struct ioctrl512x, io_control_psc2_4), 3, 0,
408 IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
409 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
411 /* FUNC2=VIU_PIX_CLK */
413 offsetof(struct ioctrl512x, io_control_psc3_4), 1, 0,
414 IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
415 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
417 /* FUNC3=GPIO24 Sets Next 2 to GPIO pads */
420 offsetof(struct ioctrl512x, io_control_psc4_0), 2, 0,
421 IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
422 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
426 offsetof(struct ioctrl512x, io_control_psc4_4), 1, 0,
427 IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(1) |
428 IO_PIN_PUE(1) | IO_PIN_ST(0) | IO_PIN_DS(0)
430 /* FUNC2=VIU_DATA5 Sets Next 5 to VIU_DATA pads */
431 /* VIU_DATA5-VIU_DATA9 */
433 offsetof(struct ioctrl512x, io_control_psc5_0), 5, 0,
434 IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
435 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
437 /* FUNC1=LPC_TSIZ1 Sets Next 2 to LPC_TSIZ pads */
438 /* LPC_TSIZ1-LPC_TSIZ2 */
440 offsetof(struct ioctrl512x, io_control_psc6_0), 2, 0,
441 IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
442 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
446 offsetof(struct ioctrl512x, io_control_psc6_4), 1, 0,
447 IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
448 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
452 offsetof(struct ioctrl512x, io_control_psc7_0), 1, 0,
453 IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
454 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
456 /* FUNC3=GPIO18 Sets Next 3 to GPIO pads */
457 /* GPIO18-GPIO19, GPT7/GPIO7 */
459 offsetof(struct ioctrl512x, io_control_psc7_2), 3, 0,
460 IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
461 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
463 /* FUNC3=GPIO0/GPT0 */
465 offsetof(struct ioctrl512x, io_control_psc8_4), 1, 0,
466 IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
467 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
469 /* FUNC3=GPIO11 Sets Next 4 to GPIO pads */
470 /* GPIO11, GPIO2, GPIO12, GPIO13 */
472 offsetof(struct ioctrl512x, io_control_psc10_3), 4, 0,
473 IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
474 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
478 offsetof(struct ioctrl512x, io_control_psc11_4), 1, 0,
479 IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
480 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
484 int checkboard (void)
486 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
488 puts("Board: PDM360NG\n");
490 /* initialize function mux & slew rate IO inter alia on IO Pins */
492 iopin_initialize(ioregs_init, ARRAY_SIZE(ioregs_init));
494 /* initialize IO_CONTROL_GP (GPIO/GPT-mux-register) */
495 setbits_be32(&im->io_ctrl.io_control_gp,
496 (1 << 0) | /* GP_MUX7->GPIO7 */
497 (1 << 5)); /* GP_MUX2->GPIO2 */
499 /* configure GPIO24 (VIU_CE), output/high */
500 setbits_be32(&im->gpio.gpdir, 0x80);
501 setbits_be32(&im->gpio.gpdat, 0x80);
506 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
507 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
508 struct node_info nodes[] = {
509 { "fsl,mpc5121-nfc", MTD_DEV_TYPE_NAND, },
510 { "cfi-flash", MTD_DEV_TYPE_NOR, },
514 #if defined(CONFIG_VIDEO)
516 * EDID block has been generated using Phoenix EDID Designer 1.3.
517 * This tool creates a text file containing:
520 * 0x 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F
521 * ------------------------------------------------
522 * 00 | 00 FF FF FF FF FF FF 00 42 C9 34 12 01 00 00 00
523 * 10 | 0A 0C 01 03 80 98 5B 78 CA 7E 50 A0 58 4E 96 25
524 * 20 | 1E 50 54 00 00 00 01 01 01 01 01 01 01 01 01 01
525 * 30 | 01 01 01 01 01 01 80 0C 20 00 31 E0 2D 10 2A 80
526 * 40 | 12 08 30 E4 10 00 00 18 00 00 00 FD 00 38 3C 1F
527 * 50 | 3C 04 0A 20 20 20 20 20 20 20 00 00 00 FF 00 50
528 * 60 | 4D 30 37 30 57 4C 33 0A 0A 0A 0A 0A 00 00 00 FF
529 * 70 | 00 41 30 30 30 30 30 30 30 30 30 30 30 31 00 D4
531 * Then this data has been manually converted to the char
534 static unsigned char edid_buf[128] = {
535 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00,
536 0x42, 0xC9, 0x34, 0x12, 0x01, 0x00, 0x00, 0x00,
537 0x0A, 0x0C, 0x01, 0x03, 0x80, 0x98, 0x5B, 0x78,
538 0xCA, 0x7E, 0x50, 0xA0, 0x58, 0x4E, 0x96, 0x25,
539 0x1E, 0x50, 0x54, 0x00, 0x00, 0x00, 0x01, 0x01,
540 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
541 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x80, 0x0C,
542 0x20, 0x00, 0x31, 0xE0, 0x2D, 0x10, 0x2A, 0x80,
543 0x12, 0x08, 0x30, 0xE4, 0x10, 0x00, 0x00, 0x18,
544 0x00, 0x00, 0x00, 0xFD, 0x00, 0x38, 0x3C, 0x1F,
545 0x3C, 0x04, 0x0A, 0x20, 0x20, 0x20, 0x20, 0x20,
546 0x20, 0x20, 0x00, 0x00, 0x00, 0xFF, 0x00, 0x50,
547 0x4D, 0x30, 0x37, 0x30, 0x57, 0x4C, 0x33, 0x0A,
548 0x0A, 0x0A, 0x0A, 0x0A, 0x00, 0x00, 0x00, 0xFF,
549 0x00, 0x41, 0x30, 0x30, 0x30, 0x30, 0x30, 0x30,
550 0x30, 0x30, 0x30, 0x30, 0x30, 0x31, 0x00, 0xD4,
554 void ft_board_setup(void *blob, bd_t *bd)
559 ft_cpu_setup(blob, bd);
560 fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
561 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
562 fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
564 #if defined(CONFIG_VIDEO)
565 fdt_add_edid(blob, "fsl,mpc5121-diu", edid_buf);
568 /* Fixup NOR FLASH mapping */
569 val[i++] = 0; /* chip select number */
570 val[i++] = 0; /* always 0 */
571 val[i++] = gd->bd->bi_flashstart;
572 val[i++] = gd->bd->bi_flashsize;
574 /* Fixup MRAM mapping */
575 val[i++] = 2; /* chip select number */
576 val[i++] = 0; /* always 0 */
577 val[i++] = CONFIG_SYS_MRAM_BASE;
578 val[i++] = CONFIG_SYS_MRAM_SIZE;
580 rc = fdt_find_and_setprop(blob, "/localbus", "ranges",
581 val, i * sizeof(u32), 1);
583 printf("Unable to update localbus ranges, err=%s\n",
586 /* Fixup reg property in NOR Flash node */
588 val[i++] = 0; /* always 0 */
589 val[i++] = 0; /* start at offset 0 */
590 val[i++] = flash_info[0].size; /* size of Bank 0 */
592 /* Second Bank available? */
593 if (flash_info[1].size > 0) {
594 val[i++] = 0; /* always 0 */
595 val[i++] = flash_info[0].size; /* offset of Bank 1 */
596 val[i++] = flash_info[1].size; /* size of Bank 1 */
599 rc = fdt_find_and_setprop(blob, "/localbus/flash", "reg",
600 val, i * sizeof(u32), 1);
602 printf("Unable to update flash reg property, err=%s\n",
605 #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
608 * If argument is NULL, set the LCD brightness to the
609 * value from "brightness" environment variable. Set
610 * the LCD brightness to the value specified by the
611 * argument otherwise. Default brightness is zero.
613 #define MAX_BRIGHTNESS 99
614 static int set_lcd_brightness(char *brightness)
616 struct stdio_dev *cop_port;
624 val = simple_strtol(brightness, NULL, 10);
626 env = getenv("brightness");
628 val = simple_strtol(env, NULL, 10);
634 if (val > MAX_BRIGHTNESS)
635 val = MAX_BRIGHTNESS;
637 sprintf(cmd_buf, "$SB;%04d;", val);
639 len = strlen(cmd_buf);
640 for (i = 1; i <= len; i++)
643 cs = (~cs + 1) & 0xff;
644 sprintf(cmd_buf + len, "%02X\n", cs);
646 /* IO Coprocessor communication */
647 cop_port = open_port(4, CONFIG_SYS_PDM360NG_COPROC_BAUDRATE);
649 printf("Error: Can't open IO Coprocessor port.\n");
653 debug("%s: cmd: %s", __func__, cmd_buf);
654 write_port(cop_port, cmd_buf);
656 * Wait for transmission and maybe response data
657 * before closing the port.
659 udelay(CONFIG_SYS_PDM360NG_COPROC_READ_DELAY);
660 memset(cmd_buf, 0, sizeof(cmd_buf));
661 len = read_port(cop_port, cmd_buf, sizeof(cmd_buf));
663 printf("Error: %s\n", cmd_buf);
670 static int cmd_lcd_brightness(cmd_tbl_t *cmdtp, int flag,
671 int argc, char * const argv[])
674 return cmd_usage(cmdtp);
676 return set_lcd_brightness(argv[1]);
679 U_BOOT_CMD(lcdbr, 2, 1, cmd_lcd_brightness,
680 "set LCD brightness",
681 "<brightness> - set LCD backlight level to <brightness>.\n"