2 * Board specific setup info
4 * (C) Copyright 2003-2004
6 * Texas Instruments, <www.ti.com>
7 * Kshitij Gupta <Kshitij@ti.com>
9 * Modified for OMAP 1610 H2 board by Nishant Kamat, Jan 2004
11 * Modified for OMAP730 P2 Board by Dave Peverley, MPC-Data Limited
12 * (http://www.mpc-data.co.uk)
14 * TODO : Tidy up and change to use system register defines
15 * from omap730.h where possible.
17 * See file CREDITS for list of people who contributed to this
20 * This program is free software; you can redistribute it and/or
21 * modify it under the terms of the GNU General Public License as
22 * published by the Free Software Foundation; either version 2 of
23 * the License, or (at your option) any later version.
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
30 * You should have received a copy of the GNU General Public License
31 * along with this program; if not, write to the Free Software
32 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
39 #if defined(CONFIG_OMAP730)
40 #include <./configs/omap730.h>
44 .word TEXT_BASE /* sdram load addr from config.mk */
48 /* Save callers address in r11 - r11 must never be modified */
51 /*------------------------------------------------------*
52 *mask all IRQs by setting all bits in the INTMR default*
53 *------------------------------------------------------*/
60 /*------------------------------------------------------*
61 * Set up ARM CLM registers (IDLECT1) *
62 *------------------------------------------------------*/
63 ldr r0, REG_ARM_IDLECT1
64 ldr r1, VAL_ARM_IDLECT1
67 /*------------------------------------------------------*
68 * Set up ARM CLM registers (IDLECT2) *
69 *------------------------------------------------------*/
70 ldr r0, REG_ARM_IDLECT2
71 ldr r1, VAL_ARM_IDLECT2
74 /*------------------------------------------------------*
75 * Set up ARM CLM registers (IDLECT3) *
76 *------------------------------------------------------*/
77 ldr r0, REG_ARM_IDLECT3
78 ldr r1, VAL_ARM_IDLECT3
82 mov r1, #0x01 /* PER_EN bit */
83 ldr r0, REG_ARM_RSTCT2
84 strh r1, [r0] /* CLKM; Peripheral reset. */
86 /* Set CLKM to Sync-Scalable */
87 /* I supposedly need to enable the dsp clock before switching */
93 subs r0, r0, #0x1 /* wait for any bubbles to finish */
99 /* a few nops to let settle */
112 /* Ramp up the clock to 96Mhz */
113 ldr r1, VAL_DPLL1_CTL
114 ldr r0, REG_DPLL1_CTL
116 ands r1, r1, #0x10 /* Check if PLL is enabled. */
117 beq lock_end /* Do not look for lock if BYPASS selected */
120 ands r1, r1, #0x01 /* Check the LOCK bit.*/
121 beq 2b /* loop until bit goes hi. */
124 /*------------------------------------------------------*
125 * Turn off the watchdog during init... *
126 *------------------------------------------------------*/
128 ldr r1, WATCHDOG_VAL1
130 ldr r1, WATCHDOG_VAL2
151 /* Set memory timings corresponding to the new clock speed */
153 /* Check execution location to determine current execution location
154 * and branch to appropriate initialization code.
156 /* Compare physical SDRAM base & current execution location. */
157 and r0, pc, #0xF0000000
160 /* Skip over EMIF-fast initialization if running from SDRAM. */
164 * Delay for SDRAM initialization.
166 mov r3, #0x1800 /* value should be checked */
168 subs r3, r3, #0x1 /* Decrement count */
171 ldr r0, REG_SDRAM_CONFIG
172 ldr r1, SDRAM_CONFIG_VAL
175 ldr r0, REG_SDRAM_MRS_LEGACY
176 ldr r1, SDRAM_MRS_VAL
183 ldr r1, VAL_TC_EMIFS_CS0_CONFIG
184 ldr r0, REG_TC_EMIFS_CS0_CONFIG
185 str r1, [r0] /* Chip Select 0 */
187 ldr r1, VAL_TC_EMIFS_CS1_CONFIG
188 ldr r0, REG_TC_EMIFS_CS1_CONFIG
189 str r1, [r0] /* Chip Select 1 */
190 ldr r1, VAL_TC_EMIFS_CS2_CONFIG
191 ldr r0, REG_TC_EMIFS_CS2_CONFIG
192 str r1, [r0] /* Chip Select 2 */
193 ldr r1, VAL_TC_EMIFS_CS3_CONFIG
194 ldr r0, REG_TC_EMIFS_CS3_CONFIG
195 str r1, [r0] /* Chip Select 3 */
197 /* 48MHz clock request for UART1 */
198 ldr r1, PERSEUS2_CONFIG_BASE
199 ldrh r0, [r1, #CONFIG_PCC_CONF]
200 orr r0, r0, #CONF_MOD_UART1_CLK_MODE_R
201 strh r0, [r1, #CONFIG_PCC_CONF]
203 /* Initialize public and private rheas
204 * - set access factor 2 on both rhea / strobe
205 * - disable write buffer on strb0, enable write buffer on strb1
208 ldr R0, REG_RHEA_PUB_CTL
209 ldr R1, REG_RHEA_PRIV_CTL
213 mov R3, #2 /* disable write buffer on strb0, enable write buffer on strb1 */
214 strh R3, [R0, #0x08] /* arm rhea control reg */
217 /* enable IRQ and FIQ */
220 bic r4, r4, #IRQ_MASK
221 bic r4, r4, #FIQ_MASK
224 /* set TAP CONF to TRI EMULATION */
226 ldr r1, [r0, #CONFIG_MODE2]
229 str r1, [r0, #CONFIG_MODE2]
231 /* set tdbgen to 1 */
233 ldr r0, PERSEUS2_CONFIG_BASE
234 ldr r1, [r0, #CONFIG_MODE1]
237 str r1, [r0, #CONFIG_MODE1]
239 #ifdef CONFIG_P2_OMAP1610
240 /* inserting additional 2 clock cycle hold time for LAN */
241 ldr r0, REG_TC_EMIFS_CS1_ADVANCED
242 ldr r1, VAL_TC_EMIFS_CS1_ADVANCED
245 /* Start MPU Timer 1 */
246 ldr r0, REG_MPU_LOAD_TIMER
247 ldr r1, VAL_MPU_LOAD_TIMER
250 ldr r0, REG_MPU_CNTL_TIMER
251 ldr r1, VAL_MPU_CNTL_TIMER
254 /* back to arch calling code */
257 /* the literal pools origin */
260 REG_TC_EMIFS_CONFIG: /* 32 bits */
262 REG_TC_EMIFS_CS0_CONFIG: /* 32 bits */
264 REG_TC_EMIFS_CS1_CONFIG: /* 32 bits */
266 REG_TC_EMIFS_CS2_CONFIG: /* 32 bits */
268 REG_TC_EMIFS_CS3_CONFIG: /* 32 bits */
271 #ifdef CONFIG_P2_OMAP730
272 REG_TC_EMIFS_CS1_ADVANCED: /* 32 bits */
276 /* MPU clock/reset/power mode control registers */
277 REG_ARM_CKCTL: /* 16 bits */
280 REG_ARM_IDLECT3: /* 16 bits */
282 REG_ARM_IDLECT2: /* 16 bits */
284 REG_ARM_IDLECT1: /* 16 bits */
287 REG_ARM_RSTCT2: /* 16 bits */
289 REG_ARM_SYSST: /* 16 bits */
291 /* DPLL control registers */
292 REG_DPLL1_CTL: /* 16 bits */
295 /* Watch Dog register */
296 /* secure watchdog stop */
299 /* watchdog write pending */
308 /* SDRAM config is: auto refresh enabled, 16 bit 4 bank,
309 counter @8192 rows, 10 ns, 8 burst */
313 REG_SDRAM_MRS_LEGACY:
324 /* Public and private rhea bridge registers definition */
332 /* EMIFF SDRAM Configuration register
333 - self refresh disable
334 - auto refresh enabled
335 - SDRAM type 64 Mb, 16 bits bus 4 banks
337 - SDRAM clock disabled
342 /* Burst full page length ; cas latency = 3 */
351 #ifdef CONFIG_P2_OMAP730
352 VAL_TC_EMIFS_CS0_CONFIG:
354 VAL_TC_EMIFS_CS1_CONFIG:
356 VAL_TC_EMIFS_CS2_CONFIG:
358 VAL_TC_EMIFS_CS3_CONFIG:
360 VAL_TC_EMIFS_CS1_ADVANCED:
384 /* Config Register vals */
385 PERSEUS2_CONFIG_BASE:
388 .equ CONFIG_PCC_CONF, 0xB4
389 .equ CONFIG_MODE1, 0x10
390 .equ CONFIG_MODE2, 0x14
391 .equ CONF_MOD_UART1_CLK_MODE_R, 0x0A
394 .equ IRQ_MASK, 0x80 /* IRQ mask value */
395 .equ FIQ_MASK, 0x40 /* FIQ mask value */