2 * Board specific setup info
5 * Texas Instruments, <www.ti.com>
6 * Richard Woodruff <r-woodruff2@ti.com>
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 #include <asm/arch/omap2420.h>
30 #include <asm/arch/mem.h>
31 #include <asm/arch/clocks.h>
34 .word TEXT_BASE /* sdram load addr from config.mk */
36 #ifdef CONFIG_PARTIAL_SRAM
38 /**************************************************************************
39 * cpy_clk_code: relocates clock code into SRAM where its safer to execute
40 * R1 = SRAM destination address.
41 *************************************************************************/
44 /* Copy DPLL code into SRAM */
45 adr r0, go_to_speed /* get addr of clock setting code */
46 mov r2, #384 /* r2 size to copy (div by 32 bytes) */
47 mov r1, r1 /* r1 <- dest address (passed in) */
48 add r2, r2, r0 /* r2 <- source end address */
50 ldmia r0!, {r3-r10} /* copy from source address [r0] */
51 stmia r1!, {r3-r10} /* copy to target address [r1] */
52 cmp r0, r2 /* until source end address [r2] */
54 mov pc, lr /* back to caller */
56 /* ****************************************************************************
57 * go_to_speed: -Moves to bypass, -Commits clock dividers, -puts dpll at speed
58 * -executed from SRAM.
59 * R0 = PRCM_CLKCFG_CTRL - addr of valid reg
60 * R1 = CM_CLKEN_PLL - addr dpll ctlr reg
62 * R3 = CM_IDLEST_CKGEN - addr dpll lock wait
63 ******************************************************************************/
66 sub sp, sp, #0x4 /* get some stack space */
67 str r4, [sp] /* save r4's value */
69 /* move into fast relock bypass */
75 ldr r8, [r4] /* wait for bypass to take effect */
80 /* set new dpll dividers _after_ in bypass */
85 /* now prepare GPMC (flash) for new dpll speed */
86 /* flash needs to be stable when we jump back to it */
95 orr r8, r8, #0x3 /* up gpmc divider */
98 /* setup to 2x loop though code. The first loop pre-loads the
99 * icache, the 2nd commits the prcm config, and locks the dpll
101 mov r4, #0x1000 /* spin spin spin */
102 mov r8, #0x4 /* first pass condition & set registers */
105 ldrne r8, [r3] /* DPLL lock check */
111 streq r8, [r0] /* commit dividers (2nd time) */
114 sub r4, r4, #0x1 /* Loop currently necessary else bad jumps */
121 streq r2, [r1] /* lock dpll (2nd time) */
124 sub r4, r4, #0x1 /* loop currently necessary else bad jumps */
131 ldreq r8, [r3] /* get lock condition for dpll */
132 cmp r8, #0x4 /* first time though? */
134 moveq r8, #0x2 /* set to dpll check condition. */
135 beq 3b /* if condition not true branch */
138 add sp, sp, #0x4 /* return stack space */
139 mov pc, lr /* back to caller, locked */
141 _go_to_speed: .word go_to_speed
143 /* these constants need to be close for PIC code */
147 .word H4_24XX_GPMC_CONFIG3_0
151 .word H4_24XX_GPMC_CONFIG4_0
157 .word CM_IDLEST_CKGEN
161 .word DPLL_VAL /* DPLL setting (300MHz default) */
166 mov r3, r0 /* save skip information */
168 ldr r0, REG_SDRC_MCFG_0
169 ldr r1, VAL_SDRC_MCFG_0
171 ldr r0, REG_SDRC_MR_0
172 ldr r1, VAL_SDRC_MR_0
174 /* a ddr needs emr1 set here */
175 ldr r0, REG_SDRC_SHARING
176 ldr r1, VAL_SDRC_SHARING
178 ldr r0, REG_SDRC_RFR_CTRL_0
179 ldr r1, VAL_SDRC_RFR_CTRL_0
182 /* little delay after init */
188 #ifdef CONFIG_PARTIAL_SRAM
190 str ip, [sp] /* stash old link register */
191 mov ip, lr /* save link reg across call */
192 mov r0, r3 /* pass skip info to s_init */
193 bl s_init /* go setup pll,mux,memory */
194 ldr ip, [sp] /* restore save ip */
195 mov lr, ip /* restore link reg */
197 /* map interrupt controller */
198 ldr r0, VAL_INTH_SETUP
199 mcr p15, 0, r0, c15, c2, 4
201 /* back to arch calling code */
204 /* the literal pools origin */
210 .word PERIFERAL_PORT_BASE
212 .word LOW_LEVEL_SRAM_STACK
224 .word VAL_H4_SDRC_SHARING
226 .word VAL_H4_SDRC_MCFG_0
228 .word VAL_H4_SDRC_MR_0
230 .word VAL_H4_SDRC_RFR_CTRL_0