3 * Texas Instruments, <www.ti.com>
4 * Richard Woodruff <r-woodruff2@ti.com>
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 #include <asm/arch/omap2420.h>
25 #include <asm/arch/bits.h>
26 #include <asm/arch/mux.h>
27 #include <asm/arch/mem.h>
28 #include <asm/arch/clocks.h>
29 #include <asm/arch/sys_proto.h>
30 #include <asm/arch/sys_info.h>
32 /************************************************************
33 * sdelay() - simple spin loop. Will be constant time as
34 * its generally used in 12MHz bypass conditions only. This
35 * is necessary until timers are accessible.
37 * not inline to increase chances its in cache when called
38 *************************************************************/
39 void sdelay (unsigned long loops)
41 __asm__ volatile ("1:\n" "subs %0, %1, #1\n"
42 "bne 1b":"=r" (loops):"0" (loops));
45 /*********************************************************************************
46 * prcm_init() - inits clocks for PRCM as defined in clocks.h (config II default).
47 * -- called from SRAM, or Flash (using temp SRAM stack).
48 *********************************************************************************/
52 void (*f_lock_pll) (u32, u32, u32, u32);
53 extern void *_end_vect, *_start;
55 f_lock_pll = (void *)((u32)&_end_vect - (u32)&_start + SRAM_VECT_CODE);
57 __raw_writel(0, CM_FCLKEN1_CORE); /* stop all clocks to reduce ringing */
58 __raw_writel(0, CM_FCLKEN2_CORE); /* may not be necessary */
59 __raw_writel(0, CM_ICLKEN1_CORE);
60 __raw_writel(0, CM_ICLKEN2_CORE);
62 __raw_writel(DPLL_OUT, CM_CLKSEL2_PLL); /* set DPLL out */
63 __raw_writel(MPU_DIV, CM_CLKSEL_MPU); /* set MPU divider */
64 __raw_writel(DSP_DIV, CM_CLKSEL_DSP); /* set dsp and iva dividers */
65 __raw_writel(GFX_DIV, CM_CLKSEL_GFX); /* set gfx dividers */
68 if (rev == CPU_2420_ES1 || rev == CPU_2422_ES1)
72 __raw_writel(div, CM_CLKSEL1_CORE);/* set L3/L4/USB/Display/Vlnc/SSi dividers */
75 if(running_in_sram()){
76 /* If running fully from SRAM this is OK. The Flash bus drops out for just a little.
77 * but then comes back. If running from Flash this sequence kills you, thus you need
78 * to run it using CONFIG_PARTIAL_SRAM.
80 __raw_writel(MODE_BYPASS_FAST, CM_CLKEN_PLL); /* go to bypass, fast relock */
81 wait_on_value(BIT0|BIT1, BIT0, CM_IDLEST_CKGEN, LDELAY); /* wait till in bypass */
83 /* set clock selection and dpll dividers. */
84 __raw_writel(DPLL_VAL, CM_CLKSEL1_PLL); /* set pll for target rate */
85 __raw_writel(COMMIT_DIVIDERS, PRCM_CLKCFG_CTRL); /* commit dividers */
87 __raw_writel(DPLL_LOCK, CM_CLKEN_PLL); /* enable dpll */
89 wait_on_value(BIT0|BIT1, BIT1, CM_IDLEST_CKGEN, LDELAY); /*wait for dpll lock */
90 }else if(running_in_flash()){
91 /* if running from flash, need to jump to small relocated code area in SRAM.
92 * This is the only safe spot to do configurations from.
94 (*f_lock_pll)(PRCM_CLKCFG_CTRL, CM_CLKEN_PLL, DPLL_LOCK, CM_IDLEST_CKGEN);
97 __raw_writel(DPLL_LOCK|APLL_LOCK, CM_CLKEN_PLL); /* enable apll */
98 wait_on_value(BIT8, BIT8, CM_IDLEST_CKGEN, LDELAY); /* wait for apll lock */
103 /********************************************************
104 * mem_ok() - test used to see if timings are correct
105 * for a part. Helps in gussing which part
106 * we are currently using.
107 *******************************************************/
111 u32 pattern = 0x12345678;
113 __raw_writel(0x0,OMAP2420_SDRC_CS0+0x400); /* clear pos A */
114 __raw_writel(pattern, OMAP2420_SDRC_CS0); /* pattern to pos B */
115 __raw_writel(0x0,OMAP2420_SDRC_CS0+4); /* remove pattern off the bus */
116 val1 = __raw_readl(OMAP2420_SDRC_CS0+0x400); /* get pos A value */
117 val2 = __raw_readl(OMAP2420_SDRC_CS0); /* get val2 */
119 if ((val1 != 0) || (val2 != pattern)) /* see if pos A value changed*/
125 /********************************************************
126 * sdrc_init() - init the sdrc chip selects CS0 and CS1
127 * - early init routines, called from flash or
129 *******************************************************/
133 do_sdrc_init(SDRC_CS0_OSET, EARLY_INIT); /* only init up first bank here */
136 /*************************************************************************
137 * do_sdrc_init(): initialize the SDRAM for use.
138 * -called from low level code with stack only.
139 * -code sets up SDRAM timing and muxing for 2422 or 2420.
140 * -optimal settings can be placed here, or redone after i2c
141 * inspection of board info
143 * This is a bit ugly, but should handle all memory moduels
144 * used with the H4. The first time though this code from s_init()
145 * we configure the first chip select. Later on we come back and
146 * will configure the 2nd chip select if it exists.
148 **************************************************************************/
149 void do_sdrc_init(u32 offset, u32 early)
151 u32 cpu, bug=0, rev, common=0, cs0=0, pmask=0, pass_type;
152 sdrc_data_t *sdata; /* do not change type */
155 static const sdrc_data_t sdrc_2422 =
157 H4_2422_SDRC_SHARING, H4_2422_SDRC_MDCFG_0_DDR, 0 , H4_2422_SDRC_ACTIM_CTRLA_0,
158 H4_2422_SDRC_ACTIM_CTRLB_0, H4_2422_SDRC_RFR_CTRL_ES1, H4_2422_SDRC_MR_0_DDR,
159 0, H4_2422_SDRC_DLLA_CTRL, H4_2422_SDRC_DLLB_CTRL
161 static const sdrc_data_t sdrc_2420 =
163 H4_2420_SDRC_SHARING, H4_2420_SDRC_MDCFG_0_DDR, H4_2420_SDRC_MDCFG_0_SDR,
164 H4_2420_SDRC_ACTIM_CTRLA_0, H4_2420_SDRC_ACTIM_CTRLB_0,
165 H4_2420_SDRC_RFR_CTRL_ES1, H4_2420_SDRC_MR_0_DDR, H4_2420_SDRC_MR_0_SDR,
166 H4_2420_SDRC_DLLA_CTRL, H4_2420_SDRC_DLLB_CTRL
169 if (offset == SDRC_CS0_OSET)
170 cs0 = common = 1; /* int regs shared between both chip select */
172 cpu = get_cpu_type();
174 /* warning generated, though code generation is correct. this may bite later,
175 * but is ok for now. there is only so much C code you can do on stack only
178 if (cpu == CPU_2422){
179 sdata = (sdrc_data_t *)&sdrc_2422;
182 sdata = (sdrc_data_t *)&sdrc_2420;
186 __asm__ __volatile__("": : :"memory"); /* limit compiler scope */
188 /* u-boot is compiled to run in DDR or SRAM at 8xxxxxxx or 4xxxxxxx.
189 * If we are running in flash prior to relocation and we use data
190 * here which is not pc relative we need to get the address correct.
191 * We need to find the current flash mapping to dress up the initial
192 * pointer load. As long as this is const data we should be ok.
194 if((early) && running_in_flash()){
195 sdata = (sdrc_data_t *)(((u32)sdata & 0x0003FFFF) | get_gpmc0_base());
196 /* NOR internal boot offset is 0x4000 from xloader signature */
197 if(running_from_internal_boot())
198 sdata = (sdrc_data_t *)((u32)sdata + 0x4000);
200 if (!early && (get_mem_type() == DDR_COMBO)) {/* combo part has a shared CKE signal, can't use feature */
202 pass_type = COMBO_DDR; /* CS1 config */
206 if (common) { /* do a SDRC reset between types to clear regs*/
207 __raw_writel(SOFTRESET, SDRC_SYSCONFIG); /* reset sdrc */
208 wait_on_value(BIT0, BIT0, SDRC_STATUS, 12000000);/* wait till reset done set */
209 __raw_writel(0, SDRC_SYSCONFIG); /* clear soft reset */
210 __raw_writel(sdata->sdrc_sharing, SDRC_SHARING);
211 __raw_writel((__raw_readl(SDRC_POWER)) & ~pmask, SDRC_POWER);
213 __raw_writel(__raw_readl(SMS_SYSCONFIG)|SMART_IDLE, SMS_SYSCONFIG);
214 __raw_writel(sdata->sdrc_sharing|SMART_IDLE, SDRC_SHARING);
215 __raw_writel((__raw_readl(SDRC_POWER)|BIT6) & ~pmask, SDRC_POWER);
219 if ((pass_type == IP_DDR) || (pass_type == STACKED)) /* (IP ddr-CS0),(2422-CS0/CS1) */
220 __raw_writel(sdata->sdrc_mdcfg_0_ddr, SDRC_MCFG_0+offset);
221 else if (pass_type == COMBO_DDR){ /* (combo-CS0/CS1) */
222 __raw_writel(H4_2420_COMBO_MDCFG_0_DDR,SDRC_MCFG_0+offset);
223 } else if (pass_type == IP_SDR){ /* ip sdr-CS0 */
224 __raw_writel(sdata->sdrc_mdcfg_0_sdr, SDRC_MCFG_0+offset);
227 if(pass_type == IP_SDR){ /* SDRAM can run full speed only rated for 105MHz*/
228 a = H4_242X_SDRC_ACTIM_CTRLA_0_100MHz;
229 b = H4_242X_SDRC_ACTIM_CTRLB_0_100MHz;
230 r = H4_2420_SDRC_RFR_CTRL;
232 a = sdata->sdrc_actim_ctrla_0;
233 b = sdata->sdrc_actim_ctrlb_0;
234 r = sdata->sdrc_rfr_ctrl;
238 __raw_writel(a, SDRC_ACTIM_CTRLA_0);
239 __raw_writel(b, SDRC_ACTIM_CTRLB_0);
241 __raw_writel(a, SDRC_ACTIM_CTRLA_1);
242 __raw_writel(b, SDRC_ACTIM_CTRLB_1);
245 __raw_writel(r, SDRC_RFR_CTRL+offset);
247 /* init sequence for mDDR/mSDR using manual commands (DDR is a bit different) */
248 __raw_writel(CMD_NOP, SDRC_MANUAL_0+offset);
249 sdelay(5000); /* susposed to be 100us per design spec for mddr/msdr */
250 __raw_writel(CMD_PRECHARGE, SDRC_MANUAL_0+offset);
251 __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0+offset);
252 __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0+offset);
255 * CSx SDRC Mode Register
256 * Burst length = (4 - DDR) (2-SDR)
260 if(pass_type == IP_SDR)
261 __raw_writel(sdata->sdrc_mr_0_sdr, SDRC_MR_0+offset);
263 __raw_writel(sdata->sdrc_mr_0_ddr, SDRC_MR_0+offset);
265 /* NOTE: ES1 242x _BUG_ DLL + External Bandwidth fix*/
267 if (rev == CPU_2420_ES1 || rev == CPU_2422_ES1){
269 __raw_writel((__raw_readl(SMS_CLASS_ARB0)|BURSTCOMPLETE_GROUP7)
270 ,SMS_CLASS_ARB0);/* enable bust complete for lcd */
272 /* enable & load up DLL with good value for 75MHz, and set phase to 90% */
273 if (common && (pass_type != IP_SDR)) {
274 __raw_writel(sdata->sdrc_dlla_ctrl, SDRC_DLLA_CTRL);
275 __raw_writel(sdata->sdrc_dlla_ctrl & ~(BIT2|bug), SDRC_DLLA_CTRL);
276 __raw_writel(sdata->sdrc_dllb_ctrl, SDRC_DLLB_CTRL);
277 __raw_writel(sdata->sdrc_dllb_ctrl & ~(BIT2|bug) , SDRC_DLLB_CTRL);
282 return; /* STACKED, other configued type */
283 ++pass_type; /* IPDDR->COMBODDR->IPSDR for CS0 */
287 /*****************************************************
288 * gpmc_init(): init gpmc bus
289 * Init GPMC for x16, MuxMode (SDRAM in x32).
290 * This code can only be executed from SRAM or SDRAM.
291 *****************************************************/
294 u32 mux=0, mtype, mwidth;
296 /* global settings */
297 __raw_writel(0x10, GPMC_SYSCONFIG); /* smart idle */
298 __raw_writel(0x0, GPMC_IRQENABLE); /* isr's sources masked */
299 __raw_writel(0x1, GPMC_TIMEOUT_CONTROL);/* timeout disable */
301 __raw_writel(0x001, GPMC_CONFIG); /* set nWP, disable limited addr */
303 __raw_writel(0x111, GPMC_CONFIG); /* set nWP, disable limited addr */
306 /* discover bus connection from sysboot */
307 if (is_gpmc_muxed() == GPMC_MUXED)
309 mtype = get_gpmc0_type();
310 mwidth = get_gpmc0_width();
313 __raw_writel(0x0, GPMC_CONFIG7_0); /* disable current map */
317 __raw_writel(H4_24XX_GPMC_CONFIG1_0|mtype|mwidth, GPMC_CONFIG1_0);
319 __raw_writel(H4_24XX_GPMC_CONFIG1_0|mux|mtype|mwidth, GPMC_CONFIG1_0);
322 #ifdef PRCM_CONFIG_III
323 __raw_writel(H4_24XX_GPMC_CONFIG2_0, GPMC_CONFIG2_0);
325 __raw_writel(H4_24XX_GPMC_CONFIG3_0, GPMC_CONFIG3_0);
326 __raw_writel(H4_24XX_GPMC_CONFIG4_0, GPMC_CONFIG4_0);
327 #ifdef PRCM_CONFIG_III
328 __raw_writel(H4_24XX_GPMC_CONFIG5_0, GPMC_CONFIG5_0);
329 __raw_writel(H4_24XX_GPMC_CONFIG6_0, GPMC_CONFIG6_0);
331 __raw_writel(H4_24XX_GPMC_CONFIG7_0, GPMC_CONFIG7_0);/* enable new mapping */
335 __raw_writel(0, GPMC_CONFIG7_1); /* disable any mapping */
337 __raw_writel(H4_24XX_GPMC_CONFIG1_1|mux, GPMC_CONFIG1_1);
338 __raw_writel(H4_24XX_GPMC_CONFIG2_1, GPMC_CONFIG2_1);
339 __raw_writel(H4_24XX_GPMC_CONFIG3_1, GPMC_CONFIG3_1);
340 __raw_writel(H4_24XX_GPMC_CONFIG4_1, GPMC_CONFIG4_1);
341 __raw_writel(H4_24XX_GPMC_CONFIG5_1, GPMC_CONFIG5_1);
342 __raw_writel(H4_24XX_GPMC_CONFIG6_1, GPMC_CONFIG6_1);
343 __raw_writel(H4_24XX_GPMC_CONFIG7_1, GPMC_CONFIG7_1); /* enable mapping */