3 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
4 * Marius Groeger <mgroeger@sysgo.de>
7 * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
10 * Texas Instruments, <www.ti.com>
11 * Kshitij Gupta <Kshitij@ti.com>
13 * Modified for OMAP 1610 H2 board by Nishant Kamat, Jan 2004
15 * See file CREDITS for list of people who contributed to this
18 * This program is free software; you can redistribute it and/or
19 * modify it under the terms of the GNU General Public License as
20 * published by the Free Software Foundation; either version 2 of
21 * the License, or (at your option) any later version.
23 * This program is distributed in the hope that it will be useful,
24 * but WITHOUT ANY WARRANTY; without even the implied warranty of
25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 * GNU General Public License for more details.
28 * You should have received a copy of the GNU General Public License
29 * along with this program; if not, write to the Free Software
30 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
35 #if defined(CONFIG_OMAP1610)
36 #include <./configs/omap1510.h>
39 #ifdef CONFIG_CS_AUTOBOOT
40 unsigned long omap_flash_base;
43 void flash__init (void);
44 void ether__init (void);
45 void set_muxconf_regs (void);
46 void peripheral_power_enable (void);
48 #define COMP_MODE_ENABLE ((unsigned int)0x0000EAEF)
50 static inline void delay (unsigned long loops)
52 __asm__ volatile ("1:\n"
54 "bne 1b":"=r" (loops):"0" (loops));
58 * Miscellaneous platform dependent initialisations
63 DECLARE_GLOBAL_DATA_PTR;
65 /* arch number of OMAP 1510-Board */
66 /* to be changed for OMAP 1610 Board */
67 gd->bd->bi_arch_number = 234;
69 /* adress of boot parameters */
70 gd->bd->bi_boot_params = 0x10000100;
72 /* Configure MUX settings */
74 peripheral_power_enable ();
76 /* this speeds up your boot a quite a bit. However to make it
77 * work, you need make sure your kernel startup flush bug is fixed.
88 int misc_init_r (void)
94 /******************************
97 ******************************/
98 void flash__init (void)
100 #define EMIFS_GlB_Config_REG 0xfffecc0c
103 #ifdef CONFIG_CS_AUTOBOOT
104 /* Check swapping of CS0 and CS3, set flash base accordingly */
105 omap_flash_base = ((*((u32 *)OMAP_EMIFS_CONFIG_REG) & 0x02) == 0) ?
106 PHYS_FLASH_1_BM0 : PHYS_FLASH_1_BM1;
108 regval = *((volatile unsigned int *) EMIFS_GlB_Config_REG);
109 /* Turn off write protection for flash devices. */
110 regval = regval | 0x0001;
111 *((volatile unsigned int *) EMIFS_GlB_Config_REG) = regval;
113 /*************************************************************
115 Description: take the Ethernet controller out of reset and wait
116 for the EEPROM load to complete.
117 *************************************************************/
118 void ether__init (void)
120 #define ETH_CONTROL_REG 0x0400030b
122 #ifdef CONFIG_H2_OMAP1610
123 #define LAN_RESET_REGISTER 0x0400001c
125 /* The debug board on which the lan chip resides may not be powered
126 * ON at the same time as the OMAP chip. So wait in a loop until the
127 * lan reset register (on the debug board) is available (powered on)
128 * and reset the lan chip.
131 *((volatile unsigned short *) LAN_RESET_REGISTER) = 0x0000;
133 *((volatile unsigned short *) LAN_RESET_REGISTER) = 0x0001;
135 } while (*((volatile unsigned short *) LAN_RESET_REGISTER) != 0x0001);
138 *((volatile unsigned short *) LAN_RESET_REGISTER) = 0x0000;
140 } while (*((volatile unsigned short *) LAN_RESET_REGISTER) != 0x0000);
143 *((volatile unsigned char *) ETH_CONTROL_REG) &= ~0x01;
147 /******************************
150 ******************************/
153 DECLARE_GLOBAL_DATA_PTR;
155 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
156 gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
161 /******************************************************
162 Routine: set_muxconf_regs
163 Description: Setting up the configuration Mux registers
164 specific to the hardware
165 *******************************************************/
166 void set_muxconf_regs (void)
168 volatile unsigned int *MuxConfReg;
169 /* set each registers to its reset value; */
171 (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_0);
172 /* setup for UART1 */
173 *MuxConfReg &= ~(0x02000000); /* bit 25 */
174 /* setup for UART2 */
175 *MuxConfReg &= ~(0x01000000); /* bit 24 */
176 /* Disable Uwire CS Hi-Z */
177 *MuxConfReg |= 0x08000000;
179 (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_3);
180 *MuxConfReg = 0x00000000;
182 (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_4);
183 *MuxConfReg = 0x00000000;
185 (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_5);
186 *MuxConfReg = 0x00000000;
188 (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_6);
189 /*setup mux for UART3 */
190 *MuxConfReg |= 0x00000001; /* bit3, 1, 0 (mux0 5,5,26) */
191 *MuxConfReg &= ~0x0000003e;
193 (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_7);
194 *MuxConfReg = 0x00000000;
196 (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_8);
197 /* Disable Uwire CS Hi-Z */
198 *MuxConfReg |= 0x00001200; /*bit 9 for CS0 12 for CS3 */
200 (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_9);
201 /* Need to turn on bits 21 and 12 in FUNC_MUX_CTRL_9 so the */
202 /* hardware will actually use TX and RTS based on bit 25 in */
203 /* FUNC_MUX_CTRL_0. I told you this thing was screwy! */
204 *MuxConfReg |= 0x00201000;
206 (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_A);
207 *MuxConfReg = 0x00000000;
209 (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_B);
210 *MuxConfReg = 0x00000000;
212 (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_C);
213 /* setup for UART2 */
214 /* Need to turn on bits 27 and 24 in FUNC_MUX_CTRL_C so the */
215 /* hardware will actually use TX and RTS based on bit 24 in */
216 /* FUNC_MUX_CTRL_0. */
217 *MuxConfReg |= 0x09000000;
219 (volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_0);
220 *MuxConfReg = 0x00000000;
222 (volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_1);
223 *MuxConfReg = 0x00000000;
224 /* mux setup for SD/MMC driver */
226 (volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_2);
227 *MuxConfReg &= 0xFFFE0FFF;
229 (volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_3);
230 *MuxConfReg = 0x00000000;
232 (volatile unsigned int *) ((unsigned int) MOD_CONF_CTRL_0);
233 /* bit 13 for MMC2 XOR_CLK */
234 *MuxConfReg &= ~(0x00002000);
235 /* bit 29 for UART 1 */
236 *MuxConfReg &= ~(0x00002000);
238 (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_0);
239 /* Configure for USB. Turn on VBUS_CTRL and VBUS_MODE. */
240 *MuxConfReg |= 0x000C0000;
242 (volatile unsigned int *) ((unsigned int)USB_TRANSCEIVER_CTRL);
243 *MuxConfReg &= ~(0x00000070);
244 *MuxConfReg &= ~(0x00000008);
245 *MuxConfReg |= 0x00000003;
246 *MuxConfReg |= 0x00000180;
248 (volatile unsigned int *) ((unsigned int) MOD_CONF_CTRL_0);
249 /* bit 17, software controls VBUS */
250 *MuxConfReg &= ~(0x00020000);
251 /* Enable USB 48 and 12M clocks */
252 *MuxConfReg |= 0x00000200;
253 *MuxConfReg &= ~(0x00000180);
254 /*2.75V for MMCSDIO1 */
256 (volatile unsigned int *) ((unsigned int) VOLTAGE_CTRL_0);
257 *MuxConfReg = 0x00001FE7;
259 (volatile unsigned int *) ((unsigned int) PU_PD_SEL_0);
260 *MuxConfReg = 0x00000000;
262 (volatile unsigned int *) ((unsigned int) PU_PD_SEL_1);
263 *MuxConfReg = 0x00000000;
265 (volatile unsigned int *) ((unsigned int) PU_PD_SEL_2);
266 *MuxConfReg = 0x00000000;
268 (volatile unsigned int *) ((unsigned int) PU_PD_SEL_3);
269 *MuxConfReg = 0x00000000;
271 (volatile unsigned int *) ((unsigned int) PU_PD_SEL_4);
272 *MuxConfReg = 0x00000000;
274 (volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_4);
275 *MuxConfReg = 0x00000000;
276 /* Turn on UART2 48 MHZ clock */
278 (volatile unsigned int *) ((unsigned int) MOD_CONF_CTRL_0);
279 *MuxConfReg |= 0x40000000;
281 (volatile unsigned int *) ((unsigned int) USB_OTG_CTRL);
282 /* setup for USB VBus detection OMAP161x */
283 *MuxConfReg |= 0x00040000; /* bit 18 */
285 (volatile unsigned int *) ((unsigned int) PU_PD_SEL_2);
286 /* PullUps for SD/MMC driver */
287 *MuxConfReg |= ~(0xFFFE0FFF);
289 (volatile unsigned int *) ((unsigned int)COMP_MODE_CTRL_0);
290 *MuxConfReg = COMP_MODE_ENABLE;
293 /******************************************************
294 Routine: peripheral_power_enable
295 Description: Enable the power for UART1
296 *******************************************************/
297 void peripheral_power_enable (void)
299 #define UART1_48MHZ_ENABLE ((unsigned short)0x0200)
300 #define SW_CLOCK_REQUEST ((volatile unsigned short *)0xFFFE0834)
302 *SW_CLOCK_REQUEST |= UART1_48MHZ_ENABLE;