2 * (C) Copyright 2013-2015
3 * NVIDIA Corporation <www.nvidia.com>
5 * SPDX-License-Identifier: GPL-2.0+
8 #ifndef _MAX77620_INIT_H_
9 #define _MAX77620_INIT_H_
11 /* MAX77620-PMIC-specific early init regs */
13 #define MAX77620_I2C_ADDR 0x78 /* or 0x3C 7-bit */
15 #define MAX77620_SD0_REG 0x16
16 #define MAX77620_SD1_REG 0x17
17 #define MAX77620_SD2_REG 0x18
18 #define MAX77620_SD3_REG 0x19
19 #define MAX77620_CNFG2SD_REG 0x22
21 #define MAX77620_CNFG1_L0_REG 0x23
22 #define MAX77620_CNFG2_L0_REG 0x24
23 #define MAX77620_CNFG1_L1_REG 0x25
24 #define MAX77620_CNFG2_L1_REG 0x26
25 #define MAX77620_CNFG1_L2_REG 0x27
26 #define MAX77620_CNFG2_L2_REG 0x28
27 #define MAX77620_CNFG1_L3_REG 0x29
28 #define MAX77620_CNFG2_L3_REG 0x2A
29 #define MAX77620_CNFG1_L4_REG 0x2B
30 #define MAX77620_CNFG2_L4_REG 0x2C
31 #define MAX77620_CNFG1_L5_REG 0x2D
32 #define MAX77620_CNFG2_L5_REG 0x2E
33 #define MAX77620_CNFG1_L6_REG 0x2F
34 #define MAX77620_CNFG2_L6_REG 0x30
35 #define MAX77620_CNFG1_L7_REG 0x31
36 #define MAX77620_CNFG2_L7_REG 0x32
37 #define MAX77620_CNFG1_L8_REG 0x33
38 #define MAX77620_CNFG2_L8_REG 0x34
39 #define MAX77620_CNFG3_LDO_REG 0x35
41 #define MAX77620_GPIO0_REG 0x36
42 #define MAX77620_GPIO1_REG 0x37
43 #define MAX77620_GPIO2_REG 0x38
44 #define MAX77620_GPIO3_REG 0x39
45 #define MAX77620_GPIO4_REG 0x3A
46 #define MAX77620_GPIO5_REG 0x3B
47 #define MAX77620_GPIO6_REG 0x3C
48 #define MAX77620_GPIO7_REG 0x3D
49 #define MAX77620_GPIO_PUE_GPIO 0x3E
50 #define MAX77620_GPIO_PDE_GPIO 0x3F
52 #define MAX77620_AME_GPIO 0x40
53 #define MAX77620_REG_ONOFF_CFG1 0x41
54 #define MAX77620_REG_ONOFF_CFG2 0x42
56 #define MAX77620_CID0_REG 0x58
57 #define MAX77620_CID1_REG 0x59
58 #define MAX77620_CID2_REG 0x5A
59 #define MAX77620_CID3_REG 0x5B
60 #define MAX77620_CID4_REG 0x5C
61 #define MAX77620_CID5_REG 0x5D
63 #define I2C_SEND_2_BYTES 0x0A02
65 void pmic_enable_cpu_vdd(void);
67 #endif /* _MAX77620_INIT_H_ */