2 * (C) Copyright 2010,2011
3 * NVIDIA Corporation <www.nvidia.com>
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 #include <asm/arch/tegra2.h>
28 #include <asm/arch/sys_proto.h>
30 #include <asm/arch/clk_rst.h>
31 #include <asm/arch/clock.h>
32 #include <asm/arch/pinmux.h>
33 #include <asm/arch/uart.h>
36 #ifdef CONFIG_TEGRA2_MMC
40 DECLARE_GLOBAL_DATA_PTR;
42 const struct tegra2_sysinfo sysinfo = {
43 CONFIG_TEGRA2_BOARD_STRING
46 #ifdef CONFIG_BOARD_EARLY_INIT_F
47 int board_early_init_f(void)
49 /* Initialize periph clocks */
52 /* Initialize periph pinmuxes */
55 /* Initialize periph GPIOs */
58 /* Init UART, scratch regs, and start CPU */
62 #endif /* EARLY_INIT */
66 * Description: init the timestamp and lastinc value
74 * Routine: clock_init_uart
75 * Description: init the PLL and clock for the UART(s)
77 static void clock_init_uart(void)
79 struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
80 struct clk_pll *pll = &clkrst->crc_pll[CLOCK_PLL_ID_PERIPH];
83 reg = readl(&pll->pll_base);
84 if (!(reg & PLL_BASE_OVRRIDE)) {
85 /* Override pllp setup for 216MHz operation. */
86 reg = (PLL_BYPASS | PLL_BASE_OVRRIDE | PLL_DIVP_VALUE);
87 reg |= (((NVRM_PLLP_FIXED_FREQ_KHZ/500) << 8) | PLL_DIVM_VALUE);
88 writel(reg, &pll->pll_base);
91 writel(reg, &pll->pll_base);
94 writel(reg, &pll->pll_base);
97 /* Now do the UART reset/clock enable */
98 #if defined(CONFIG_TEGRA2_ENABLE_UARTA)
99 /* Assert UART reset and enable clock */
100 reset_set_enable(PERIPH_ID_UART1, 1);
101 clock_enable(PERIPH_ID_UART1);
103 /* Enable pllp_out0 to UART */
104 reg = readl(&clkrst->crc_clk_src_uarta);
105 reg &= 0x3FFFFFFF; /* UARTA_CLK_SRC = 00, PLLP_OUT0 */
106 writel(reg, &clkrst->crc_clk_src_uarta);
111 /* De-assert reset to UART */
112 reset_set_enable(PERIPH_ID_UART1, 0);
113 #endif /* CONFIG_TEGRA2_ENABLE_UARTA */
114 #if defined(CONFIG_TEGRA2_ENABLE_UARTD)
115 /* Assert UART reset and enable clock */
116 reset_set_enable(PERIPH_ID_UART4, 1);
117 clock_enable(PERIPH_ID_UART4);
119 /* Enable pllp_out0 to UART */
120 reg = readl(&clkrst->crc_clk_src_uartd);
121 reg &= 0x3FFFFFFF; /* UARTD_CLK_SRC = 00, PLLP_OUT0 */
122 writel(reg, &clkrst->crc_clk_src_uartd);
127 /* De-assert reset to UART */
128 reset_set_enable(PERIPH_ID_UART4, 0);
129 #endif /* CONFIG_TEGRA2_ENABLE_UARTD */
133 * Routine: pin_mux_uart
134 * Description: setup the pin muxes/tristate values for the UART(s)
136 static void pin_mux_uart(void)
138 struct pmux_tri_ctlr *pmt = (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
141 #if defined(CONFIG_TEGRA2_ENABLE_UARTA)
142 reg = readl(&pmt->pmt_ctl_c);
143 reg &= 0xFFF0FFFF; /* IRRX_/IRTX_SEL [19:16] = 00 UARTA */
144 writel(reg, &pmt->pmt_ctl_c);
146 reg = readl(&pmt->pmt_tri_a);
147 reg &= ~Z_IRRX; /* Z_IRRX = normal (0) */
148 reg &= ~Z_IRTX; /* Z_IRTX = normal (0) */
149 writel(reg, &pmt->pmt_tri_a);
150 #endif /* CONFIG_TEGRA2_ENABLE_UARTA */
151 #if defined(CONFIG_TEGRA2_ENABLE_UARTD)
152 reg = readl(&pmt->pmt_ctl_b);
153 reg &= 0xFFFFFFF3; /* GMC_SEL [3:2] = 00, UARTD */
154 writel(reg, &pmt->pmt_ctl_b);
156 reg = readl(&pmt->pmt_tri_a);
157 reg &= ~Z_GMC; /* Z_GMC = normal (0) */
158 writel(reg, &pmt->pmt_tri_a);
159 #endif /* CONFIG_TEGRA2_ENABLE_UARTD */
163 * Routine: clock_init_mmc
164 * Description: init the PLL and clocks for the SDMMC controllers
166 static void clock_init_mmc(void)
168 struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
171 /* Do the SDMMC resets/clock enables */
172 reset_set_enable(PERIPH_ID_SDMMC4, 1);
173 clock_enable(PERIPH_ID_SDMMC4);
175 /* Enable pllp_out0 to SDMMC4 */
176 reg = readl(&clkrst->crc_clk_src_sdmmc4);
177 reg &= 0x3FFFFF00; /* SDMMC4_CLK_SRC = 00, PLLP_OUT0 */
178 reg |= (10 << 1); /* n-1, 11-1 shl 1 */
179 writel(reg, &clkrst->crc_clk_src_sdmmc4);
182 * As per the Tegra2 TRM, section 5.3.4:
183 * 'Wait 2 us for the clock to flush through the pipe/logic'
187 reset_set_enable(PERIPH_ID_SDMMC4, 1);
189 reset_set_enable(PERIPH_ID_SDMMC3, 1);
190 clock_enable(PERIPH_ID_SDMMC3);
192 /* Enable pllp_out0 to SDMMC4, set divisor to 11 for 20MHz */
193 reg = readl(&clkrst->crc_clk_src_sdmmc3);
194 reg &= 0x3FFFFF00; /* SDMMC3_CLK_SRC = 00, PLLP_OUT0 */
195 reg |= (10 << 1); /* n-1, 11-1 shl 1 */
196 writel(reg, &clkrst->crc_clk_src_sdmmc3);
201 reset_set_enable(PERIPH_ID_SDMMC3, 0);
205 * Routine: pin_mux_mmc
206 * Description: setup the pin muxes/tristate values for the SDMMC(s)
208 static void pin_mux_mmc(void)
210 struct pmux_tri_ctlr *pmt = (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
214 /* config 2, x8 on 2nd set of pins */
215 reg = readl(&pmt->pmt_ctl_a);
216 reg |= (3 << 16); /* ATB_SEL [17:16] = 11 SDIO4 */
217 writel(reg, &pmt->pmt_ctl_a);
218 reg = readl(&pmt->pmt_ctl_b);
219 reg |= (3 << 0); /* GMA_SEL [1:0] = 11 SDIO4 */
220 writel(reg, &pmt->pmt_ctl_b);
221 reg = readl(&pmt->pmt_ctl_d);
222 reg |= (3 << 0); /* GME_SEL [1:0] = 11 SDIO4 */
223 writel(reg, &pmt->pmt_ctl_d);
225 reg = readl(&pmt->pmt_tri_a);
226 reg &= ~Z_ATB; /* Z_ATB = normal (0) */
227 reg &= ~Z_GMA; /* Z_GMA = normal (0) */
228 writel(reg, &pmt->pmt_tri_a);
229 reg = readl(&pmt->pmt_tri_b);
230 reg &= ~Z_GME; /* Z_GME = normal (0) */
231 writel(reg, &pmt->pmt_tri_b);
234 /* SDIO3_CLK, SDIO3_CMD, SDIO3_DAT[3:0] */
235 reg = readl(&pmt->pmt_ctl_d);
237 reg |= (2 << 10); /* SDB_SEL [11:10] = 01 SDIO3 */
238 reg |= (2 << 12); /* SDC_SEL [13:12] = 01 SDIO3 */
239 reg |= (2 << 14); /* SDD_SEL [15:14] = 01 SDIO3 */
240 writel(reg, &pmt->pmt_ctl_d);
242 reg = readl(&pmt->pmt_tri_b);
243 reg &= ~Z_SDC; /* Z_SDC = normal (0) */
244 reg &= ~Z_SDD; /* Z_SDD = normal (0) */
245 writel(reg, &pmt->pmt_tri_b);
246 reg = readl(&pmt->pmt_tri_d);
247 reg &= ~Z_SDB; /* Z_SDB = normal (0) */
248 writel(reg, &pmt->pmt_tri_d);
252 * Routine: clock_init
253 * Description: Do individual peripheral clock reset/enables
255 void clock_init(void)
261 * Routine: pinmux_init
262 * Description: Do individual peripheral pinmux configs
264 void pinmux_init(void)
271 * Description: Do individual peripheral GPIO configs
279 * Routine: board_init
280 * Description: Early hardware init.
284 /* boot param addr */
285 gd->bd->bi_boot_params = (NV_PA_SDRAM_BASE + 0x100);
290 #ifdef CONFIG_TEGRA2_MMC
291 /* this is a weak define that we are overriding */
292 int board_mmc_init(bd_t *bd)
294 debug("board_mmc_init called\n");
295 /* Enable clocks, muxes, etc. for SDMMC controllers */
299 debug("board_mmc_init: init eMMC\n");
300 /* init dev 0, eMMC chip, with 4-bit bus */
301 tegra2_mmc_init(0, 4);
303 debug("board_mmc_init: init SD slot\n");
304 /* init dev 1, SD slot, with 4-bit bus */
305 tegra2_mmc_init(1, 4);
310 /* this is a weak define that we are overriding */
311 int board_mmc_getcd(u8 *cd, struct mmc *mmc)
313 debug("board_mmc_getcd called\n");
315 * Hard-code CD presence for now. Need to add GPIO inputs
316 * for Seaboard & Harmony (& Kaen/Aebl/Wario?)