2 * board/mx1ads/syncflash.c
5 * Techware Information Technology, Inc.
6 * http://www.techware.com.tw/
8 * Ming-Len Wu <minglen_wu@techware.com.tw>
10 * SPDX-License-Identifier: GPL-2.0+
14 /*#include <mc9328.h>*/
15 #include <asm/arch/imx-regs.h>
17 typedef unsigned long * p_u32;
19 /* 4Mx16x2 IAM=0 CSD1 */
21 flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
23 /* Following Setting is for CSD1 */
24 #define SFCTL 0x00221004
25 #define reg_SFCTL __REG(SFCTL)
27 #define SYNCFLASH_A10 (0x00100000)
29 #define CMD_NORMAL (0x81020300) /* Normal Mode */
30 #define CMD_PREC (CMD_NORMAL + 0x10000000) /* Precharge Command */
31 #define CMD_AUTO (CMD_NORMAL + 0x20000000) /* Auto Refresh Command */
32 #define CMD_LMR (CMD_NORMAL + 0x30000000) /* Load Mode Register Command */
33 #define CMD_LCR (CMD_NORMAL + 0x60000000) /* LCR Command */
34 #define CMD_PROGRAM (CMD_NORMAL + 0x70000000)
36 #define MODE_REG_VAL (CONFIG_SYS_FLASH_BASE+0x0008CC00) /* Cas Latency 3 */
39 #define LCR_READSTATUS (0x0001C000) /* 0x70 */
40 #define LCR_ERASE_CONFIRM (0x00008000) /* 0x20 */
41 #define LCR_ERASE_NVMODE (0x0000C000) /* 0x30 */
42 #define LCR_PROG_NVMODE (0x00028000) /* 0xA0 */
43 #define LCR_SR_CLEAR (0x00014000) /* 0x50 */
45 /* Get Status register */
49 reg_SFCTL = CMD_PROGRAM;
50 tmp = __REG(CONFIG_SYS_FLASH_BASE);
52 reg_SFCTL = CMD_NORMAL;
54 reg_SFCTL = CMD_LCR; /* Activate LCR Mode */
55 __REG(CONFIG_SYS_FLASH_BASE + LCR_SR_CLEAR);
60 /* check if SyncFlash is ready */
66 if ((tmp & 0x00800000) && (tmp & 0x001C0000)) {
67 printf ("SyncFlash Error code %08x\n",tmp);
70 if ((tmp & 0x00000080) && (tmp & 0x0000001C)) {
71 printf ("SyncFlash Error code %08x\n",tmp);
74 if (tmp == 0x00800080) /* Test Bit 7 of SR */
80 /* Issue the precharge all command */
81 void SF_PrechargeAll(void) {
83 /* Set Precharge Command */
85 /* Issue Precharge All Command */
86 __REG(CONFIG_SYS_FLASH_BASE + SYNCFLASH_A10);
89 /* set SyncFlash to normal mode */
90 void SF_Normal(void) {
94 reg_SFCTL = CMD_NORMAL;
98 void SF_Erase(u32 RowAddress) {
100 reg_SFCTL = CMD_NORMAL;
103 reg_SFCTL = CMD_PREC;
106 reg_SFCTL = CMD_LCR; /* Set LCR mode */
107 __REG(RowAddress + LCR_ERASE_CONFIRM) = 0; /* Issue Erase Setup Command */
109 reg_SFCTL = CMD_NORMAL; /* return to Normal mode */
110 __REG(RowAddress) = 0xD0D0D0D0; /* Confirm */
115 void SF_NvmodeErase(void) {
118 reg_SFCTL = CMD_LCR; /* Set to LCR mode */
119 __REG(CONFIG_SYS_FLASH_BASE + LCR_ERASE_NVMODE) = 0; /* Issue Erase Nvmode Reg Command */
121 reg_SFCTL = CMD_NORMAL; /* Return to Normal mode */
122 __REG(CONFIG_SYS_FLASH_BASE + LCR_ERASE_NVMODE) = 0xC0C0C0C0; /* Confirm */
127 void SF_NvmodeWrite(void) {
130 reg_SFCTL = CMD_LCR; /* Set to LCR mode */
131 __REG(CONFIG_SYS_FLASH_BASE+LCR_PROG_NVMODE) = 0; /* Issue Program Nvmode reg command */
133 reg_SFCTL = CMD_NORMAL; /* Return to Normal mode */
134 __REG(CONFIG_SYS_FLASH_BASE+LCR_PROG_NVMODE) = 0xC0C0C0C0; /* Confirm not needed */
137 /****************************************************************************************/
139 ulong flash_init(void) {
142 /* Turn on CSD1 for negating RESETSF of SyncFLash */
144 reg_SFCTL |= 0x80000000; /* enable CSD1 for SyncFlash */
147 reg_SFCTL = CMD_LMR; /* Set Load Mode Register Command */
148 __REG(MODE_REG_VAL); /* Issue Load Mode Register Command */
154 flash_info[i].flash_id = FLASH_MAN_MT | FLASH_MT28S4M16LC;
156 flash_info[i].size = FLASH_BANK_SIZE;
157 flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT;
159 memset(flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT);
161 for (j = 0; j < flash_info[i].sector_count; j++) {
162 flash_info[i].start[j] = CONFIG_SYS_FLASH_BASE + j * 0x00100000;
165 flash_protect(FLAG_PROTECT_SET,
166 CONFIG_SYS_FLASH_BASE,
167 CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1,
170 flash_protect(FLAG_PROTECT_SET,
172 CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1,
175 return FLASH_BANK_SIZE;
178 void flash_print_info (flash_info_t *info) {
182 switch (info->flash_id & FLASH_VENDMASK) {
183 case (FLASH_MAN_MT & FLASH_VENDMASK):
187 printf("Unknown Vendor ");
191 switch (info->flash_id & FLASH_TYPEMASK) {
192 case (FLASH_MT28S4M16LC & FLASH_TYPEMASK):
193 printf("2x FLASH_MT28S4M16LC (16MB Total)\n");
196 printf("Unknown Chip Type\n");
201 printf(" Size: %ld MB in %d Sectors\n",
202 info->size >> 20, info->sector_count);
204 printf(" Sector Start Addresses: ");
206 for (i = 0; i < info->sector_count; i++) {
210 printf (" %08lX%s", info->start[i],
211 info->protect[i] ? " (RO)" : " ");
217 /*-----------------------------------------------------------------------*/
219 int flash_erase (flash_info_t *info, int s_first, int s_last) {
220 int iflag, cflag, prot, sect;
223 /* first look for protection bits */
225 if (info->flash_id == FLASH_UNKNOWN)
226 return ERR_UNKNOWN_FLASH_TYPE;
228 if ((s_first < 0) || (s_first > s_last))
231 if ((info->flash_id & FLASH_VENDMASK) != (FLASH_MAN_MT & FLASH_VENDMASK))
232 return ERR_UNKNOWN_FLASH_VENDOR;
236 for (sect = s_first; sect <= s_last; ++sect) {
237 if (info->protect[sect])
242 printf("protected!\n");
243 return ERR_PROTECTED;
246 * Disable interrupts which might cause a timeout
247 * here. Remember that our exception vectors are
248 * at address 0 in the flash, and we don't want a
249 * (ticker) exception to happen while the flash
250 * chip is in programming mode.
253 cflag = icache_status();
255 iflag = disable_interrupts();
257 /* Start erase on unprotected sectors */
258 for (sect = s_first; sect <= s_last && !ctrlc(); sect++) {
260 printf("Erasing sector %2d ... ", sect);
262 /* arm simple, non interrupt dependent timer */
269 SF_Erase(CONFIG_SYS_FLASH_BASE + (0x0100000 * sect));
276 printf("User Interrupt!\n");
287 /*-----------------------------------------------------------------------
288 * Copy memory to flash.
291 int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) {
294 for(i = 0; i < cnt; i += 4) {
298 reg_SFCTL = CMD_PROGRAM; /* Enter SyncFlash Program mode */
299 __REG(addr + i) = __REG((u32)src + i);