2 * GNU General Public License for more details.
4 * MATRIX Vision GmbH / June 2002-Nov 2003
17 u32 get_BoardType (void);
19 #define PCI_CONFIG(b,d,f,r) cpu_to_le32(0x80000000 | ((b&0xff)<<16) \
24 int mv_pci_read (int bus, int dev, int func, int reg)
26 *(u32 *) (0xfec00cf8) = PCI_CONFIG (bus, dev, func, reg);
28 return cpu_to_le32 (*(u32 *) (0xfee00cfc));
33 return (mv_pci_read (0, 0xe, 0, 0) == 0x06801095 ? 0 : 1);
36 void init_2nd_DUART (void)
38 NS16550_t console = (NS16550_t) CFG_NS16550_COM2;
39 int clock_divisor = CFG_NS16550_CLK / 16 / CONFIG_BAUDRATE;
41 *(u8 *) (0xfc004511) = 0x1;
42 NS16550_init (console, clock_divisor);
44 void hw_watchdog_reset (void)
46 if (get_BoardType () == 0) {
47 *(u32 *) (0xff000005) = 0;
53 DECLARE_GLOBAL_DATA_PTR;
54 ulong busfreq = get_bus_freq (0);
56 u32 BoardType = get_BoardType ();
57 char *BoardName[2] = { "mvBlueBOX", "mvBlueLYNX" };
63 printf ("U-Boot (%s) running on mvBLUE device.\n", MV_VERSION);
64 printf (" Found %s running at %s MHz memory clock.\n",
65 BoardName[BoardType], strmhz (buf, busfreq));
69 if ((p = getenv ("console_nr")) != NULL) {
70 unsigned long con_nr = simple_strtoul (p, NULL, 10) & 3;
72 bd->bi_baudrate &= ~3;
73 bd->bi_baudrate |= con_nr & 3;
78 long int initdram (int board_type)
85 size = get_ram_size(CFG_SDRAM_BASE, CFG_MAX_RAM_SIZE);
87 new_bank0_end = size - 1;
88 mear1 = mpc824x_mpc107_getreg(MEAR1);
89 emear1 = mpc824x_mpc107_getreg(EMEAR1);
90 mear1 = (mear1 & 0xFFFFFF00) |
91 ((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT);
92 emear1 = (emear1 & 0xFFFFFF00) |
93 ((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT);
94 mpc824x_mpc107_setreg(MEAR1, mear1);
95 mpc824x_mpc107_setreg(EMEAR1, emear1);
100 /* ------------------------------------------------------------------------- */
101 u8 *dhcp_vendorex_prep (u8 * e)
105 /* DHCP vendor-class-identifier = 60 */
106 if ((ptr = getenv ("dhcp_vendor-class-identifier"))) {
112 /* my DHCP_CLIENT_IDENTIFIER = 61 */
113 if ((ptr = getenv ("dhcp_client_id"))) {
122 u8 *dhcp_vendorex_proc (u8 * popt)
127 /* ------------------------------------------------------------------------- */
130 * Initialize PCI Devices
133 void pci_mvblue_clear_base (struct pci_controller *hose, pci_dev_t dev)
137 printf ("clear base @ dev/func 0x%02x/0x%02x ... ", PCI_DEV (dev),
139 for (cnt = 0; cnt < 6; cnt++)
140 pci_hose_write_config_dword (hose, dev, 0x10 + (4 * cnt),
145 void duart_setup (u32 base, u16 divisor)
147 printf ("duart setup ...");
148 out_8 ((u8 *) (CFG_ISA_IO + base + 3), 0x80);
149 out_8 ((u8 *) (CFG_ISA_IO + base + 0), divisor & 0xff);
150 out_8 ((u8 *) (CFG_ISA_IO + base + 1), divisor >> 8);
151 out_8 ((u8 *) (CFG_ISA_IO + base + 3), 0x03);
152 out_8 ((u8 *) (CFG_ISA_IO + base + 4), 0x03);
153 out_8 ((u8 *) (CFG_ISA_IO + base + 2), 0x07);
157 void pci_mvblue_fixup_irq_behind_bridge (struct pci_controller *hose,
158 pci_dev_t bridge, unsigned char irq)
162 unsigned short vendor, class;
164 pci_hose_read_config_byte (hose, bridge, PCI_SECONDARY_BUS, &bus);
165 for (d = PCI_BDF (bus, 0, 0);
166 d < PCI_BDF (bus, PCI_MAX_PCI_DEVICES - 1,
167 PCI_MAX_PCI_FUNCTIONS - 1);
168 d += PCI_BDF (0, 0, 1)) {
169 pci_hose_read_config_word (hose, d, PCI_VENDOR_ID, &vendor);
170 if (vendor != 0xffff && vendor != 0x0000) {
171 pci_hose_read_config_word (hose, d, PCI_CLASS_DEVICE,
173 if (class == PCI_CLASS_BRIDGE_PCI)
174 pci_mvblue_fixup_irq_behind_bridge (hose, d,
177 pci_hose_write_config_byte (hose, d,
184 #define MV_MAX_PCI_BUSSES 3
187 void pci_mvblue_fixup_irq (struct pci_controller *hose, pci_dev_t dev)
189 unsigned char line = 0xff;
190 unsigned short class;
192 if (PCI_BUS (dev) == 0) {
193 switch (PCI_DEV (dev)) {
195 if (get_BoardType () == 0) {
204 pci_hose_write_config_byte (hose, dev, 0x8a, 0x20);
207 /* mvBB: Slot0 (Grabber) */
208 pci_hose_read_config_word (hose, dev,
209 PCI_CLASS_DEVICE, &class);
210 if (class == PCI_CLASS_BRIDGE_PCI) {
211 pci_mvblue_fixup_irq_behind_bridge (hose, dev,
219 pci_hose_read_config_word (hose, dev,
220 PCI_CLASS_DEVICE, &class);
221 if (class == PCI_CLASS_BRIDGE_PCI) {
222 pci_mvblue_fixup_irq_behind_bridge (hose, dev,
229 printf ("***pci_scan: illegal dev = 0x%08x\n",
234 pci_hose_write_config_byte (hose, dev, PCI_INTERRUPT_LINE,
239 struct pci_controller hose = {
240 fixup_irq:pci_mvblue_fixup_irq
243 void pci_init_board (void)
245 pci_mpc824x_init (&hose);