1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (c) 2018 Microsemi Corporation
8 #include <asm/addrspace.h>
10 #include <environment.h>
14 DECLARE_GLOBAL_DATA_PTR;
17 BOARD_TYPE_PCB120 = 0xAABBCC00,
21 void external_cs_manage(struct udevice *dev, bool enable)
23 u32 cs = spi_chip_select(dev);
24 /* IF_SI0_OWNER, select the owner of the SI interface
25 * Encoding: 0: SI Slave
27 * 2: SI Master Controller
30 writel(ICPU_SW_MODE_SW_PIN_CTRL_MODE |
31 ICPU_SW_MODE_SW_SPI_CS(BIT(cs)), BASE_CFG + ICPU_SW_MODE);
32 clrsetbits_le32(BASE_CFG + ICPU_GENERAL_CTRL,
33 ICPU_GENERAL_CTRL_IF_SI_OWNER_M,
34 ICPU_GENERAL_CTRL_IF_SI_OWNER(2));
36 writel(0, BASE_CFG + ICPU_SW_MODE);
37 clrsetbits_le32(BASE_CFG + ICPU_GENERAL_CTRL,
38 ICPU_GENERAL_CTRL_IF_SI_OWNER_M,
39 ICPU_GENERAL_CTRL_IF_SI_OWNER(1));
43 void board_debug_uart_init(void)
45 /* too early for the pinctrl driver, so configure the UART pins here */
46 mscc_gpio_set_alternate(6, 1);
47 mscc_gpio_set_alternate(7, 1);
50 int board_early_init_r(void)
52 /* Prepare SPI controller to be used in master mode */
53 writel(0, BASE_CFG + ICPU_SW_MODE);
54 clrsetbits_le32(BASE_CFG + ICPU_GENERAL_CTRL,
55 ICPU_GENERAL_CTRL_IF_SI_OWNER_M,
56 ICPU_GENERAL_CTRL_IF_SI_OWNER(2));
58 /* Address of boot parameters */
59 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE;
62 if (IS_ENABLED(CONFIG_LED))
68 static void do_board_detect(void)
73 mscc_gpio_set_alternate(14, 1);
74 mscc_gpio_set_alternate(15, 1);
75 if (mscc_phy_rd(1, 0, 0, &dummy) == 0)
76 gd->board_type = BOARD_TYPE_PCB120;
78 gd->board_type = BOARD_TYPE_PCB123;
81 #if defined(CONFIG_MULTI_DTB_FIT)
82 int board_fit_config_name_match(const char *name)
84 if (gd->board_type == BOARD_TYPE_PCB120 &&
85 strcmp(name, "ocelot_pcb120") == 0)
88 if (gd->board_type == BOARD_TYPE_PCB123 &&
89 strcmp(name, "ocelot_pcb123") == 0)
96 #if defined(CONFIG_DTB_RESELECT)
97 int embedded_dtb_select(void)