1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (c) 2018 Microsemi Corporation
8 #include <asm/addrspace.h>
10 #include <environment.h>
15 DECLARE_GLOBAL_DATA_PTR;
18 BOARD_TYPE_PCB120 = 0xAABBCC00,
22 void mscc_switch_reset(bool enter)
24 /* Nasty workaround to avoid GPIO19 (DDR!) being reset */
25 mscc_gpio_set_alternate(19, 2);
27 debug("applying SwC reset\n");
29 writel(ICPU_RESET_CORE_RST_PROTECT, BASE_CFG + ICPU_RESET);
30 writel(PERF_SOFT_RST_SOFT_CHIP_RST, BASE_DEVCPU_GCB + PERF_SOFT_RST);
32 if (wait_for_bit_le32(BASE_DEVCPU_GCB + PERF_SOFT_RST,
33 PERF_SOFT_RST_SOFT_CHIP_RST, false, 5000, false))
34 pr_err("Tiemout while waiting for switch reset\n");
37 * Reset GPIO19 mode back as regular GPIO, output, high (DDR
38 * not reset) (Order is important)
40 setbits_le32(BASE_DEVCPU_GCB + PERF_GPIO_OE, BIT(19));
41 writel(BIT(19), BASE_DEVCPU_GCB + PERF_GPIO_OUT_SET);
42 mscc_gpio_set_alternate(19, 0);
45 void board_debug_uart_init(void)
47 /* too early for the pinctrl driver, so configure the UART pins here */
48 mscc_gpio_set_alternate(6, 1);
49 mscc_gpio_set_alternate(7, 1);
52 int board_early_init_r(void)
54 /* Prepare SPI controller to be used in master mode */
55 writel(0, BASE_CFG + ICPU_SW_MODE);
56 clrsetbits_le32(BASE_CFG + ICPU_GENERAL_CTRL,
57 ICPU_GENERAL_CTRL_IF_SI_OWNER_M,
58 ICPU_GENERAL_CTRL_IF_SI_OWNER(2));
60 /* Address of boot parameters */
61 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE;
64 if (IS_ENABLED(CONFIG_LED))
70 static void do_board_detect(void)
75 mscc_gpio_set_alternate(14, 1);
76 mscc_gpio_set_alternate(15, 1);
77 if (mscc_phy_rd(1, 0, 0, &dummy) == 0)
78 gd->board_type = BOARD_TYPE_PCB120;
80 gd->board_type = BOARD_TYPE_PCB123;
83 #if defined(CONFIG_MULTI_DTB_FIT)
84 int board_fit_config_name_match(const char *name)
86 if (gd->board_type == BOARD_TYPE_PCB120 &&
87 strcmp(name, "ocelot_pcb120") == 0)
90 if (gd->board_type == BOARD_TYPE_PCB123 &&
91 strcmp(name, "ocelot_pcb123") == 0)
98 #if defined(CONFIG_DTB_RESELECT)
99 int embedded_dtb_select(void)