3 * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 #include <asm/processor.h>
31 #include <stdio_dev.h>
32 #include "../common/isa.h"
33 #include "../common/common_util.h"
35 DECLARE_GLOBAL_DATA_PTR;
42 /* stdlib.h causes some compatibility problems; should fixe these! -- wd */
43 #ifndef __ldiv_t_defined
45 long int quot; /* Quotient */
46 long int rem; /* Remainder */
48 extern ldiv_t ldiv (long int __numer, long int __denom);
50 # define __ldiv_t_defined 1
58 SDRAM_UNSUPPORTED_ERR,
63 const unsigned char mode;
64 const unsigned char row;
65 const unsigned char col;
66 const unsigned char bank;
69 static const SDRAM_SETUP sdram_setup_table[] = {
88 static const unsigned char cal_indextable[] = {
94 * translate ns.ns/10 coding of SPD timing values
95 * into 10 ps unit values
98 unsigned short NS10to10PS (unsigned char spd_byte, unsigned char spd_version)
100 unsigned short ns, ns10;
102 /* isolate upper nibble */
103 ns = (spd_byte >> 4) & 0x0F;
104 /* isolate lower nibble */
105 ns10 = (spd_byte & 0x0F);
107 return (ns * 100 + ns10 * 10);
111 * translate ns.ns/4 coding of SPD timing values
112 * into 10 ps unit values
115 unsigned short NS4to10PS (unsigned char spd_byte, unsigned char spd_version)
117 unsigned short ns, ns4;
119 /* isolate upper 6 bits */
120 ns = (spd_byte >> 2) & 0x3F;
121 /* isloate lower 2 bits */
122 ns4 = (spd_byte & 0x03);
124 return (ns * 100 + ns4 * 25);
128 * translate ns coding of SPD timing values
129 * into 10 ps unit values
132 unsigned short NSto10PS (unsigned char spd_byte)
134 return (spd_byte * 100);
137 void SDRAM_err (const char *s)
140 (void) get_clocks ();
146 serial_puts ("\n enable SDRAM_DEBUG for more info\n");
153 void write_hex (unsigned char i)
160 serial_putc (cc + 55);
162 serial_putc (cc + 48);
165 serial_putc (cc + 55);
167 serial_putc (cc + 48);
170 void write_4hex (unsigned long val)
172 write_hex ((unsigned char) (val >> 24));
173 write_hex ((unsigned char) (val >> 16));
174 write_hex ((unsigned char) (val >> 8));
175 write_hex ((unsigned char) val);
180 int board_early_init_f (void)
182 unsigned char datain[128];
183 unsigned long sdram_size = 0;
184 SDRAM_SETUP *t = (SDRAM_SETUP *) sdram_setup_table;
185 unsigned long memclk;
186 unsigned long tmemclk = 0;
187 unsigned long tmp, bank, baseaddr, bank_size;
189 unsigned char rows, cols, banks, sdram_banks, density;
190 unsigned char supported_cal, trp_clocks, trcd_clocks, tras_clocks,
192 unsigned char cal_index, cal_val, spd_version, spd_chksum;
193 unsigned char buf[8];
195 unsigned char tctp_clocks;
198 /* set up the config port */
199 mtdcr (EBC0_CFGADDR, PB7AP);
200 mtdcr (EBC0_CFGDATA, CONFIG_PORT_AP);
201 mtdcr (EBC0_CFGADDR, PB7CR);
202 mtdcr (EBC0_CFGDATA, CONFIG_PORT_CR);
204 memclk = get_bus_freq (tmemclk);
205 tmemclk = 1000000000 / (memclk / 100); /* in 10 ps units */
208 (void) get_clocks ();
211 serial_puts ("\nstart SDRAM Setup\n");
214 /* Read Serial Presence Detect Information */
215 i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
216 for (i = 0; i < 128; i++)
218 i2c_read(SPD_EEPROM_ADDRESS,0,1,datain,128);
220 serial_puts ("\ni2c_read returns ");
226 for (i = 0; i < 128; i++) {
227 write_hex (datain[i]);
229 if (((i + 1) % 16) == 0)
235 for (i = 0; i < 63; i++) {
236 spd_chksum += datain[i];
238 if (datain[63] != spd_chksum) {
240 serial_puts ("SPD chksum: 0x");
241 write_hex (datain[63]);
242 serial_puts (" != calc. chksum: 0x");
243 write_hex (spd_chksum);
246 SDRAM_err ("SPD checksum Error");
248 /* SPD seems to be ok, use it */
250 /* get SPD version */
251 spd_version = datain[62];
253 /* do some sanity checks on the kind of RAM */
254 if ((datain[0] < 0x80) || /* less than 128 valid bytes in SPD */
255 (datain[2] != 0x04) || /* if not SDRAM */
256 (!((datain[6] == 0x40) || (datain[6] == 0x48))) || /* or not (64 Bit or 72 Bit) */
257 (datain[7] != 0x00) || (datain[8] != 0x01) || /* or not LVTTL signal levels */
258 (datain[126] == 0x66)) /* or a 66MHz modules */
259 SDRAM_err ("unsupported SDRAM");
261 serial_puts ("SDRAM sanity ok\n");
264 /* get number of rows/cols/banks out of byte 3+4+5 */
269 /* get number of SDRAM banks out of byte 17 and
270 supported CAS latencies out of byte 18 */
271 sdram_banks = datain[17];
272 supported_cal = datain[18] & ~0x81;
274 while (t->mode != 0) {
275 if ((t->row == rows) && (t->col == cols)
276 && (t->bank == sdram_banks))
282 serial_puts ("rows: ");
284 serial_puts (" cols: ");
286 serial_puts (" banks: ");
288 serial_puts (" mode: ");
293 SDRAM_err ("unsupported SDRAM");
294 /* get tRP, tRCD, tRAS and density from byte 27+29+30+31 */
296 serial_puts ("tRP: ");
297 write_hex (datain[27]);
298 serial_puts ("\ntRCD: ");
299 write_hex (datain[29]);
300 serial_puts ("\ntRAS: ");
301 write_hex (datain[30]);
305 trp_clocks = (NSto10PS (datain[27]) + (tmemclk - 1)) / tmemclk;
306 trcd_clocks = (NSto10PS (datain[29]) + (tmemclk - 1)) / tmemclk;
307 tras_clocks = (NSto10PS (datain[30]) + (tmemclk - 1)) / tmemclk;
308 density = datain[31];
310 /* trc_clocks is sum of trp_clocks + tras_clocks */
311 trc_clocks = trp_clocks + tras_clocks;
314 /* ctp = ((trp + tras) - trp - trcd) => tras - trcd */
316 ((NSto10PS (datain[30]) - NSto10PS (datain[29])) +
317 (tmemclk - 1)) / tmemclk;
319 serial_puts ("c_RP: ");
320 write_hex (trp_clocks);
321 serial_puts ("\nc_RCD: ");
322 write_hex (trcd_clocks);
323 serial_puts ("\nc_RAS: ");
324 write_hex (tras_clocks);
325 serial_puts ("\nc_RC: (RP+RAS): ");
326 write_hex (trc_clocks);
327 serial_puts ("\nc_CTP: ((RP+RAS)-RP-RCD): ");
328 write_hex (tctp_clocks);
329 serial_puts ("\nt_CTP: RAS - RCD: ");
331 char) ((NSto10PS (datain[30]) -
332 NSto10PS (datain[29])) >> 8));
333 write_hex ((unsigned char) (NSto10PS (datain[30]) - NSto10PS (datain[29])));
334 serial_puts ("\ntmemclk: ");
335 write_hex ((unsigned char) (tmemclk >> 8));
336 write_hex ((unsigned char) (tmemclk));
342 for (i = 6, cal_index = 0; (i > 0) && (cal_index < 3); i--) {
343 /* is this CAS latency supported ? */
344 if ((supported_cal >> i) & 0x01) {
345 buf[0] = datain[cal_indextable[cal_index]];
347 if (NS10to10PS (buf[0], spd_version) <= tmemclk)
350 /* SPD bytes 25+26 have another format */
351 if (NS4to10PS (buf[0], spd_version) <= tmemclk)
358 serial_puts ("CAL: ");
359 write_hex (cal_val + 1);
364 SDRAM_err ("unsupported SDRAM");
366 /* get SDRAM timing register */
367 mtdcr (SDRAM0_CFGADDR, SDRAM0_TR);
368 tmp = mfdcr (SDRAM0_CFGDATA) & ~0x018FC01F;
369 /* insert CASL value */
370 /* tmp |= ((unsigned long)cal_val) << 23; */
371 tmp |= ((unsigned long) cal_val) << 23;
372 /* insert PTA value */
373 tmp |= ((unsigned long) (trp_clocks - 1)) << 18;
374 /* insert CTP value */
375 /* tmp |= ((unsigned long)(trc_clocks - trp_clocks - trcd_clocks - 1)) << 16; */
376 tmp |= ((unsigned long) (trc_clocks - trp_clocks - trcd_clocks)) << 16;
377 /* insert LDF (always 01) */
378 tmp |= ((unsigned long) 0x01) << 14;
379 /* insert RFTA value */
380 tmp |= ((unsigned long) (trc_clocks - 4)) << 2;
381 /* insert RCD value */
382 tmp |= ((unsigned long) (trcd_clocks - 1)) << 0;
385 serial_puts ("sdtr: ");
390 /* write SDRAM timing register */
391 mtdcr (SDRAM0_CFGADDR, SDRAM0_TR);
392 mtdcr (SDRAM0_CFGDATA, tmp);
393 baseaddr = CONFIG_SYS_SDRAM_BASE;
394 bank_size = (((unsigned long) density) << 22) / 2;
395 /* insert AM value */
396 tmp = ((unsigned long) t->mode - 1) << 13;
397 /* insert SZ value; */
400 tmp |= ((unsigned long) 0x00) << 17;
403 tmp |= ((unsigned long) 0x01) << 17;
406 tmp |= ((unsigned long) 0x02) << 17;
409 tmp |= ((unsigned long) 0x03) << 17;
412 tmp |= ((unsigned long) 0x04) << 17;
415 tmp |= ((unsigned long) 0x05) << 17;
418 tmp |= ((unsigned long) 0x06) << 17;
421 SDRAM_err ("unsupported SDRAM");
423 /* get SDRAM bank 0 register */
424 mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);
425 bank = mfdcr (SDRAM0_CFGDATA) & ~0xFFCEE001;
426 bank |= (baseaddr | tmp | 0x01);
428 serial_puts ("bank0: baseaddr: ");
429 write_4hex (baseaddr);
430 serial_puts (" banksize: ");
431 write_4hex (bank_size);
432 serial_puts (" mb0cf: ");
436 baseaddr += bank_size;
437 sdram_size += bank_size;
439 /* write SDRAM bank 0 register */
440 mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);
441 mtdcr (SDRAM0_CFGDATA, bank);
443 /* get SDRAM bank 1 register */
444 mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR);
445 bank = mfdcr (SDRAM0_CFGDATA) & ~0xFFCEE001;
449 serial_puts ("bank1: baseaddr: ");
450 write_4hex (baseaddr);
451 serial_puts (" banksize: ");
452 write_4hex (bank_size);
455 bank |= (baseaddr | tmp | 0x01);
456 baseaddr += bank_size;
457 sdram_size += bank_size;
460 serial_puts (" mb1cf: ");
464 /* write SDRAM bank 1 register */
465 mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR);
466 mtdcr (SDRAM0_CFGDATA, bank);
468 /* get SDRAM bank 2 register */
469 mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR);
470 bank = mfdcr (SDRAM0_CFGDATA) & ~0xFFCEE001;
472 bank |= (baseaddr | tmp | 0x01);
475 serial_puts ("bank2: baseaddr: ");
476 write_4hex (baseaddr);
477 serial_puts (" banksize: ");
478 write_4hex (bank_size);
479 serial_puts (" mb2cf: ");
484 baseaddr += bank_size;
485 sdram_size += bank_size;
487 /* write SDRAM bank 2 register */
488 mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR);
489 mtdcr (SDRAM0_CFGDATA, bank);
491 /* get SDRAM bank 3 register */
492 mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR);
493 bank = mfdcr (SDRAM0_CFGDATA) & ~0xFFCEE001;
496 serial_puts ("bank3: baseaddr: ");
497 write_4hex (baseaddr);
498 serial_puts (" banksize: ");
499 write_4hex (bank_size);
503 bank |= (baseaddr | tmp | 0x01);
504 baseaddr += bank_size;
505 sdram_size += bank_size;
509 serial_puts (" mb3cf: ");
514 /* write SDRAM bank 3 register */
515 mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR);
516 mtdcr (SDRAM0_CFGDATA, bank);
519 /* get SDRAM refresh interval register */
520 mtdcr (SDRAM0_CFGADDR, SDRAM0_RTR);
521 tmp = mfdcr (SDRAM0_CFGDATA) & ~0x3FF80000;
523 if (tmemclk < NSto10PS (16))
528 /* write SDRAM refresh interval register */
529 mtdcr (SDRAM0_CFGADDR, SDRAM0_RTR);
530 mtdcr (SDRAM0_CFGDATA, tmp);
532 /* enable SDRAM controller with no ECC, 32-bit SDRAM width, 16 byte burst */
533 mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG);
534 tmp = (mfdcr (SDRAM0_CFGDATA) & ~0xFFE00000) | 0x80E00000;
535 mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG);
536 mtdcr (SDRAM0_CFGDATA, tmp);
539 /*-------------------------------------------------------------------------+
540 | Interrupt controller setup for the PIP405 board.
541 | Note: IRQ 0-15 405GP internally generated; active high; level sensitive
542 | IRQ 16 405GP internally generated; active low; level sensitive
544 | IRQ 25 (EXT IRQ 0) SouthBridg; active low; level sensitive
545 | IRQ 26 (EXT IRQ 1) NMI: active low; level sensitive
546 | IRQ 27 (EXT IRQ 2) SMI: active Low; level sensitive
547 | IRQ 28 (EXT IRQ 3) PCI SLOT 3; active low; level sensitive
548 | IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
549 | IRQ 30 (EXT IRQ 5) PCI SLOT 1; active low; level sensitive
550 | IRQ 31 (EXT IRQ 6) PCI SLOT 0; active low; level sensitive
551 | Note for PIP405 board:
552 | An interrupt taken for the SouthBridge (IRQ 25) indicates that
553 | the Interrupt Controller in the South Bridge has caused the
554 | interrupt. The IC must be read to determine which device
555 | caused the interrupt.
557 +-------------------------------------------------------------------------*/
558 mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
559 mtdcr (UIC0ER, 0x00000000); /* disable all ints */
560 mtdcr (UIC0CR, 0x00000000); /* set all to be non-critical (for now) */
561 mtdcr (UIC0PR, 0xFFFFFF80); /* set int polarities */
562 mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */
563 mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */
564 mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
570 /* ------------------------------------------------------------------------- */
573 * Check Board Identity:
576 int checkboard (void)
581 backup_t *b = (backup_t *) s;
585 i = getenv_f("serial#", (char *)s, 32);
586 if ((i == 0) || strncmp ((char *)s, "PIP405", 6)) {
587 get_backup_values (b);
588 if (strncmp (b->signature, "MPL\0", 4) != 0) {
589 puts ("### No HW ID - assuming PIP405");
591 b->serial_name[6] = 0;
592 printf ("%s SN: %s", b->serial_name,
597 printf ("%s SN: %s", s, &s[7]);
599 bc = in8 (CONFIG_PORT_ADDR);
600 printf (" Boot Config: 0x%x\n", bc);
605 /* ------------------------------------------------------------------------- */
606 /* ------------------------------------------------------------------------- */
608 initdram(int board_type) reads EEPROM via I2c. EEPROM contains all of
609 the necessary info for SDRAM controller configuration
611 /* ------------------------------------------------------------------------- */
612 /* ------------------------------------------------------------------------- */
613 static int test_dram (unsigned long ramsize);
615 phys_size_t initdram (int board_type)
617 unsigned long bank_reg[4], tmp, bank_size;
619 unsigned long TotalSize;
622 /* since the DRAM controller is allready set up,
623 * calculate the size with the bank registers
625 mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);
626 bank_reg[0] = mfdcr (SDRAM0_CFGDATA);
627 mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR);
628 bank_reg[1] = mfdcr (SDRAM0_CFGDATA);
629 mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR);
630 bank_reg[2] = mfdcr (SDRAM0_CFGDATA);
631 mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR);
632 bank_reg[3] = mfdcr (SDRAM0_CFGDATA);
634 for (i = 0; i < 4; i++) {
635 if ((bank_reg[i] & 0x1) == 0x1) {
636 tmp = (bank_reg[i] >> 17) & 0x7;
637 bank_size = 4 << tmp;
638 TotalSize += bank_size;
643 printf ("single-sided DIMM ");
645 printf ("double-sided DIMM ");
646 test_dram (TotalSize * 1024 * 1024);
647 /* bank 2 (SDRAM Clock 2) is not usable if 133MHz SDRAM IF */
649 if (gd->cpu_clk > 220000000)
651 return (TotalSize * 1024 * 1024);
654 /* ------------------------------------------------------------------------- */
657 static int test_dram (unsigned long ramsize)
659 /* not yet implemented */
664 extern flash_info_t flash_info[]; /* info for FLASH chips */
666 int misc_init_r (void)
668 /* adjust flash start and size as well as the offset */
669 gd->bd->bi_flashstart=0-flash_info[0].size;
670 gd->bd->bi_flashsize=flash_info[0].size-CONFIG_SYS_MONITOR_LEN;
671 gd->bd->bi_flashoffset=0;
673 /* if PIP405 has booted from PCI, reset CCR0[24] as described in errata PCI_18 */
674 if (mfdcr(CPC0_PSR) & PSR_ROM_LOC)
675 mtspr(SPRN_CCR0, (mfspr(SPRN_CCR0) & ~0x80));
680 /***************************************************************************
681 * some helping routines
684 int overwrite_console (void)
686 return (in8 (CONFIG_PORT_ADDR) & 0x1); /* return TRUE if console should be overwritten */
690 extern int isa_init (void);
693 void print_pip405_rev (void)
695 unsigned char part, vers, cfg;
697 part = in8 (PLD_PART_REG);
698 vers = in8 (PLD_VERS_REG);
699 cfg = in8 (PLD_BOARD_CFG_REG);
700 printf ("Rev: PIP405-%d Rev %c PLD%d %d PLD%d %d\n",
701 16 - ((cfg >> 4) & 0xf), (cfg & 0xf) + 'A', part & 0xf,
702 vers & 0xf, (part >> 4) & 0xf, (vers >> 4) & 0xf);
705 extern void check_env(void);
708 int last_stage_init (void)
712 stdio_print_current_devices ();
717 /************************************************************************
719 ************************************************************************/
720 void print_pip405_info (void)
722 unsigned char part, vers, cfg, ledu, sysman, flashcom, can, serpwr,
723 compwr, nicvga, scsirst;
725 part = in8 (PLD_PART_REG);
726 vers = in8 (PLD_VERS_REG);
727 cfg = in8 (PLD_BOARD_CFG_REG);
728 ledu = in8 (PLD_LED_USER_REG);
729 sysman = in8 (PLD_SYS_MAN_REG);
730 flashcom = in8 (PLD_FLASH_COM_REG);
731 can = in8 (PLD_CAN_REG);
732 serpwr = in8 (PLD_SER_PWR_REG);
733 compwr = in8 (PLD_COM_PWR_REG);
734 nicvga = in8 (PLD_NIC_VGA_REG);
735 scsirst = in8 (PLD_SCSI_RST_REG);
736 printf ("PLD Part %d version %d\n",
737 part & 0xf, vers & 0xf);
738 printf ("PLD Part %d version %d\n",
739 (part >> 4) & 0xf, (vers >> 4) & 0xf);
740 printf ("Board Revision %c\n", (cfg & 0xf) + 'A');
741 printf ("Population Options %d %d %d %d\n",
742 (cfg >> 4) & 0x1, (cfg >> 5) & 0x1,
743 (cfg >> 6) & 0x1, (cfg >> 7) & 0x1);
744 printf ("User LED0 %s User LED1 %s\n",
745 ((ledu & 0x1) == 0x1) ? "on" : "off",
746 ((ledu & 0x2) == 0x2) ? "on" : "off");
747 printf ("Additionally Options %d %d\n",
748 (ledu >> 2) & 0x1, (ledu >> 3) & 0x1);
749 printf ("User Config Switch %d %d %d %d\n",
750 (ledu >> 4) & 0x1, (ledu >> 5) & 0x1,
751 (ledu >> 6) & 0x1, (ledu >> 7) & 0x1);
752 switch (sysman & 0x3) {
754 printf ("PCI Clocks are running\n");
757 printf ("PCI Clocks are stopped in POS State\n");
760 printf ("PCI Clocks are stopped when PCI_STP# is asserted\n");
763 printf ("PCI Clocks are stopped\n");
766 switch ((sysman >> 2) & 0x3) {
768 printf ("Main Clocks are running\n");
771 printf ("Main Clocks are stopped in POS State\n");
775 printf ("PCI Clocks are stopped\n");
778 printf ("INIT asserts %sINT2# (SMI)\n",
779 ((sysman & 0x10) == 0x10) ? "" : "not ");
780 printf ("INIT asserts %sINT1# (NMI)\n",
781 ((sysman & 0x20) == 0x20) ? "" : "not ");
782 printf ("INIT occured %d\n", (sysman >> 6) & 0x1);
783 printf ("SER1 is routed to %s\n",
784 ((flashcom & 0x1) == 0x1) ? "RS485" : "RS232");
785 printf ("COM2 is routed to %s\n",
786 ((flashcom & 0x2) == 0x2) ? "RS485" : "RS232");
787 printf ("RS485 is configured as %s duplex\n",
788 ((flashcom & 0x4) == 0x4) ? "full" : "half");
789 printf ("RS485 is connected to %s\n",
790 ((flashcom & 0x8) == 0x8) ? "COM1" : "COM2");
791 printf ("SER1 uses handshakes %s\n",
792 ((flashcom & 0x10) == 0x10) ? "DTR/DSR" : "RTS/CTS");
793 printf ("Bootflash is %swriteprotected\n",
794 ((flashcom & 0x20) == 0x20) ? "not " : "");
795 printf ("Bootflash VPP is %s\n",
796 ((flashcom & 0x40) == 0x40) ? "on" : "off");
797 printf ("Bootsector is %swriteprotected\n",
798 ((flashcom & 0x80) == 0x80) ? "not " : "");
799 switch ((can) & 0x3) {
801 printf ("CAN Controller is on address 0x1000..0x10FF\n");
804 printf ("CAN Controller is on address 0x8000..0x80FF\n");
807 printf ("CAN Controller is on address 0xE000..0xE0FF\n");
810 printf ("CAN Controller is disabled\n");
813 switch ((can >> 2) & 0x3) {
815 printf ("CAN Controller Reset is ISA Reset\n");
818 printf ("CAN Controller Reset is ISA Reset and POS State\n");
822 printf ("CAN Controller is in reset\n");
825 if (((can >> 4) < 3) || ((can >> 4) == 8) || ((can >> 4) == 13))
826 printf ("CAN Interrupt is disabled\n");
828 printf ("CAN Interrupt is ISA INT%d\n", (can >> 4) & 0xf);
829 switch (serpwr & 0x3) {
831 printf ("SER0 Drivers are enabled\n");
834 printf ("SER0 Drivers are disabled in the POS state\n");
838 printf ("SER0 Drivers are disabled\n");
841 switch ((serpwr >> 2) & 0x3) {
843 printf ("SER1 Drivers are enabled\n");
846 printf ("SER1 Drivers are disabled in the POS state\n");
850 printf ("SER1 Drivers are disabled\n");
853 switch (compwr & 0x3) {
855 printf ("COM1 Drivers are enabled\n");
858 printf ("COM1 Drivers are disabled in the POS state\n");
862 printf ("COM1 Drivers are disabled\n");
865 switch ((compwr >> 2) & 0x3) {
867 printf ("COM2 Drivers are enabled\n");
870 printf ("COM2 Drivers are disabled in the POS state\n");
874 printf ("COM2 Drivers are disabled\n");
877 switch ((nicvga) & 0x3) {
879 printf ("PHY is running\n");
882 printf ("PHY is in Power save mode in POS state\n");
886 printf ("PHY is in Power save mode\n");
889 switch ((nicvga >> 2) & 0x3) {
891 printf ("VGA is running\n");
894 printf ("VGA is in Power save mode in POS state\n");
898 printf ("VGA is in Power save mode\n");
901 printf ("PHY is %sreseted\n", ((nicvga & 0x10) == 0x10) ? "" : "not ");
902 printf ("VGA is %sreseted\n", ((nicvga & 0x20) == 0x20) ? "" : "not ");
903 printf ("Reserved Configuration is %d %d\n", (nicvga >> 6) & 0x1,
904 (nicvga >> 7) & 0x1);
905 switch ((scsirst) & 0x3) {
907 printf ("SCSI Controller is running\n");
910 printf ("SCSI Controller is in Power save mode in POS state\n");
914 printf ("SCSI Controller is in Power save mode\n");
917 printf ("SCSI termination is %s\n",
918 ((scsirst & 0x4) == 0x4) ? "disabled" : "enabled");
919 printf ("SCSI Controller is %sreseted\n",
920 ((scsirst & 0x10) == 0x10) ? "" : "not ");
921 printf ("IDE disks are %sreseted\n",
922 ((scsirst & 0x20) == 0x20) ? "" : "not ");
923 printf ("ISA Bus is %sreseted\n",
924 ((scsirst & 0x40) == 0x40) ? "" : "not ");
925 printf ("Super IO is %sreseted\n",
926 ((scsirst & 0x80) == 0x80) ? "" : "not ");
929 void user_led0 (unsigned char on)
932 out8 (PLD_LED_USER_REG, (in8 (PLD_LED_USER_REG) | 0x1));
934 out8 (PLD_LED_USER_REG, (in8 (PLD_LED_USER_REG) & 0xfe));
937 void user_led1 (unsigned char on)
940 out8 (PLD_LED_USER_REG, (in8 (PLD_LED_USER_REG) | 0x2));
942 out8 (PLD_LED_USER_REG, (in8 (PLD_LED_USER_REG) & 0xfd));
945 void ide_set_reset (int idereset)
947 /* if reset = 1 IDE reset will be asserted */
948 unsigned char resreg;
950 resreg = in8 (PLD_SCSI_RST_REG);
957 out8 (PLD_SCSI_RST_REG, resreg);