3 * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 * How do I program the SDRAM Timing Register (SDRAM0_TR) for a specific SDRAM or DIMM?
30 * As an example, consider a case where PC133 memory with CAS Latency equal to 2 is being
31 * used with a 200MHz 405GP. For a typical 128Mb, PC133 SDRAM, the relevant minimum
32 * parameters from the datasheet are:
33 * Tclk = 7.5ns (CL = 2)
39 * If we are operating the 405GP with the MemClk output frequency set to 100 MHZ, the clock
40 * period is 10ns and the parameters needed for the Timing Register are:
41 * CASL = CL = 2 clock cycles
42 * PTA = Trp = 15ns / 10ns = 2 clock cycles
43 * CTP = Trc - Trcd - Trp = (60ns - 15ns - 15ns) / 10ns= 3 clock cycles
44 * LDF = 2 clock cycles (but can be extended to meet board-level timing)
45 * RFTA = Trfc = 66ns / 10ns= 7 clock cycles
46 * RCD = Trcd = 15ns / 10ns= 2 clock cycles
48 * The actual bit settings in the register would be:
57 * If Trfc is not specified in the datasheet for PC100 or PC133 memory, set RFTA = Trc
58 * instead. Figure 24 in the PC SDRAM Specification Rev. 1.7 shows refresh to active delay
59 * defined as Trc rather than Trfc.
60 * When using DIMM modules, most but not all of the required timing parameters can be read
61 * from the Serial Presence Detect (SPD) EEPROM on the module. Specifically, Trc and Trfc
62 * are not available from the EEPROM
67 #include <asm/processor.h>
68 #include <405gp_i2c.h>
70 #include "../common/common_util.h"
72 extern block_dev_desc_t * scsi_get_dev(int dev);
73 extern block_dev_desc_t * ide_get_dev(int dev);
80 /* stdlib.h causes some compatibility problems; should fixe these! -- wd */
81 #ifndef __ldiv_t_defined
83 long int quot; /* Quotient */
84 long int rem; /* Remainder */
86 extern ldiv_t ldiv (long int __numer, long int __denom);
87 # define __ldiv_t_defined 1
91 #define PLD_PART_REG PER_PLD_ADDR + 0
92 #define PLD_VERS_REG PER_PLD_ADDR + 1
93 #define PLD_BOARD_CFG_REG PER_PLD_ADDR + 2
94 #define PLD_IRQ_REG PER_PLD_ADDR + 3
95 #define PLD_COM_MODE_REG PER_PLD_ADDR + 4
96 #define PLD_EXT_CONF_REG PER_PLD_ADDR + 5
98 #define MEGA_BYTE (1024*1024)
101 unsigned char boardtype; /* Board revision and Population Options */
102 unsigned char cal; /* cas Latency (will be programmend as cal-1) */
103 unsigned char trp; /* datain27 in clocks */
104 unsigned char trcd; /* datain29 in clocks */
105 unsigned char tras; /* datain30 in clocks */
106 unsigned char tctp; /* tras - trcd in clocks */
107 unsigned char am; /* Address Mod (will be programmed as am-1) */
108 unsigned char sz; /* log binary => Size = (4MByte<<sz) 5 = 128, 4 = 64, 3 = 32, 2 = 16, 1=8 */
109 unsigned char ecc; /* if true, ecc is enabled */
112 const sdram_t sdram_table[] = {
113 { 0x0f, /* Rev A, 128MByte -1 Board */
114 3, /* Case Latenty = 3 */
115 3, /* trp 20ns / 7.5 ns datain[27] */
116 3, /* trcd 20ns /7.5 ns (datain[29]) */
117 6, /* tras 44ns /7.5 ns (datain[30]) */
118 4, /* tcpt 44 - 20ns = 24ns */
119 3, /* Address Mode = 3 */
121 1}, /* ECC enabled */
122 { 0x07, /* Rev A, 64MByte -2 Board */
123 3, /* Case Latenty = 3 */
124 3, /* trp 20ns / 7.5 ns datain[27] */
125 3, /* trcd 20ns /7.5 ns (datain[29]) */
126 6, /* tras 44ns /7.5 ns (datain[30]) */
127 4, /* tcpt 44 - 20ns = 24ns */
128 2, /* Address Mode = 2 */
130 1}, /* ECC enabled */
131 { 0xff, /* terminator */
141 void SDRAM_err (const char *s)
144 DECLARE_GLOBAL_DATA_PTR;
146 (void) get_clocks ();
152 serial_puts ("\n enable SDRAM_DEBUG for more info\n");
157 unsigned char get_board_revcfg (void)
159 out8 (PER_BOARD_ADDR, 0);
160 return (in8 (PER_BOARD_ADDR));
166 void write_hex (unsigned char i)
173 serial_putc (cc + 55);
175 serial_putc (cc + 48);
178 serial_putc (cc + 55);
180 serial_putc (cc + 48);
183 void write_4hex (unsigned long val)
185 write_hex ((unsigned char) (val >> 24));
186 write_hex ((unsigned char) (val >> 16));
187 write_hex ((unsigned char) (val >> 8));
188 write_hex ((unsigned char) val);
194 int init_sdram (void)
196 DECLARE_GLOBAL_DATA_PTR;
198 unsigned long tmp, baseaddr;
200 unsigned char trp_clocks,
205 unsigned char cal_val;
207 unsigned long pbcr, sdram_tim, sdram_bank;
210 i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);
211 (void) get_clocks ();
214 serial_puts ("\nInitializing SDRAM, Please stand by");
215 mtdcr (ebccfga, pb0cr); /* get cs0 config reg */
216 pbcr = mfdcr (ebccfgd);
217 if ((pbcr & 0x00002000) == 0) {
218 /* MPS Boot, set up the flash */
219 mtdcr (ebccfga, pb1ap);
220 mtdcr (ebccfgd, FLASH_AP);
221 mtdcr (ebccfga, pb1cr);
222 mtdcr (ebccfgd, FLASH_CR);
224 /* Flash boot, set up the MPS */
225 mtdcr (ebccfga, pb1ap);
226 mtdcr (ebccfgd, MPS_AP);
227 mtdcr (ebccfga, pb1cr);
228 mtdcr (ebccfgd, MPS_CR);
230 /* set up UART0 (CS2) and UART1 (CS3) */
231 mtdcr (ebccfga, pb2ap);
232 mtdcr (ebccfgd, UART0_AP);
233 mtdcr (ebccfga, pb2cr);
234 mtdcr (ebccfgd, UART0_CR);
235 mtdcr (ebccfga, pb3ap);
236 mtdcr (ebccfgd, UART1_AP);
237 mtdcr (ebccfga, pb3cr);
238 mtdcr (ebccfgd, UART1_CR);
241 mtdcr (ebccfga, pb7ap);
242 mtdcr (ebccfgd, PLD_AP);
243 mtdcr (ebccfga, pb7cr);
244 mtdcr (ebccfgd, PLD_CR);
245 /* set up the board rev reg */
246 mtdcr (ebccfga, pb5ap);
247 mtdcr (ebccfgd, BOARD_AP);
248 mtdcr (ebccfga, pb5cr);
249 mtdcr (ebccfgd, BOARD_CR);
253 out8 (PER_BOARD_ADDR, 0);
254 bc = in8 (PER_BOARD_ADDR);
255 serial_puts ("\nBoard Rev: ");
257 serial_puts (" (PLD=");
258 bc = in8 (PLD_BOARD_CFG_REG);
262 bc = get_board_revcfg ();
264 serial_puts ("\nstart SDRAM Setup\n");
265 serial_puts ("\nBoard Rev: ");
270 baseaddr = CFG_SDRAM_BASE;
271 while (sdram_table[i].sz != 0xff) {
272 if (sdram_table[i].boardtype == bc)
276 if (sdram_table[i].boardtype != bc)
277 SDRAM_err ("No SDRAM table found for this board!!!\n");
279 serial_puts (" found table ");
283 cal_val = sdram_table[i].cal - 1; /* Cas Latency */
284 trp_clocks = sdram_table[i].trp; /* 20ns / 7.5 ns datain[27] */
285 trcd_clocks = sdram_table[i].trcd; /* 20ns /7.5 ns (datain[29]) */
286 tras_clocks = sdram_table[i].tras; /* 44ns /7.5 ns (datain[30]) */
287 /* ctp = ((trp + tras) - trp - trcd) => tras - trcd */
288 tctp_clocks = sdram_table[i].tctp; /* 44 - 20ns = 24ns */
289 /* trc_clocks is sum of trp_clocks + tras_clocks */
290 trc_clocks = trp_clocks + tras_clocks;
291 /* get SDRAM timing register */
292 mtdcr (memcfga, mem_sdtr1);
293 sdram_tim = mfdcr (memcfgd) & ~0x018FC01F;
294 /* insert CASL value */
295 sdram_tim |= ((unsigned long) (cal_val)) << 23;
296 /* insert PTA value */
297 sdram_tim |= ((unsigned long) (trp_clocks - 1)) << 18;
298 /* insert CTP value */
300 ((unsigned long) (trc_clocks - trp_clocks -
302 /* insert LDF (always 01) */
303 sdram_tim |= ((unsigned long) 0x01) << 14;
304 /* insert RFTA value */
305 sdram_tim |= ((unsigned long) (trc_clocks - 4)) << 2;
306 /* insert RCD value */
307 sdram_tim |= ((unsigned long) (trcd_clocks - 1)) << 0;
309 tmp = ((unsigned long) (sdram_table[i].am - 1) << 13); /* AM = 3 */
310 /* insert SZ value; */
311 tmp |= ((unsigned long) sdram_table[i].sz << 17);
312 /* get SDRAM bank 0 register */
313 mtdcr (memcfga, mem_mb0cf);
314 sdram_bank = mfdcr (memcfgd) & ~0xFFCEE001;
315 sdram_bank |= (baseaddr | tmp | 0x01);
318 serial_puts ("sdtr: ");
319 write_4hex (sdram_tim);
323 /* write SDRAM timing register */
324 mtdcr (memcfga, mem_sdtr1);
325 mtdcr (memcfgd, sdram_tim);
328 serial_puts ("mb0cf: ");
329 write_4hex (sdram_bank);
333 /* write SDRAM bank 0 register */
334 mtdcr (memcfga, mem_mb0cf);
335 mtdcr (memcfgd, sdram_bank);
337 if (get_bus_freq (tmp) > 110000000) { /* > 110MHz */
338 /* get SDRAM refresh interval register */
339 mtdcr (memcfga, mem_rtr);
340 tmp = mfdcr (memcfgd) & ~0x3FF80000;
343 /* get SDRAM refresh interval register */
344 mtdcr (memcfga, mem_rtr);
345 tmp = mfdcr (memcfgd) & ~0x3FF80000;
348 /* write SDRAM refresh interval register */
349 mtdcr (memcfga, mem_rtr);
350 mtdcr (memcfgd, tmp);
351 /* enable ECC if used */
353 if (sdram_table[i].ecc) {
354 /* disable checking for all banks */
356 serial_puts ("disable ECC.. ");
358 mtdcr (memcfga, mem_ecccf);
359 tmp = mfdcr (memcfgd);
360 tmp &= 0xff0fffff; /* disable all banks */
361 mtdcr (memcfga, mem_ecccf);
362 /* set up SDRAM Controller with ECC enabled */
364 serial_puts ("setup SDRAM Controller.. ");
366 mtdcr (memcfgd, tmp);
367 mtdcr (memcfga, mem_mcopt1);
368 tmp = (mfdcr (memcfgd) & ~0xFFE00000) | 0x90800000;
369 mtdcr (memcfga, mem_mcopt1);
370 mtdcr (memcfgd, tmp);
373 serial_puts ("fill the memory..\n");
376 /* now, fill all the memory */
377 tmp = ((4 * MEGA_BYTE) << sdram_table[i].sz);
378 p = (unsigned long) 0;
379 while ((unsigned long) p < tmp) {
381 if (!((unsigned long) p % 0x00800000)) /* every 8MByte */
389 serial_puts ("enable ECC\n");
392 mtdcr (memcfga, mem_ecccf);
393 tmp = mfdcr (memcfgd);
394 tmp |= 0x00800000; /* enable bank 0 */
395 mtdcr (memcfgd, tmp);
400 /* enable SDRAM controller with no ECC, 32-bit SDRAM width, 16 byte burst */
401 mtdcr (memcfga, mem_mcopt1);
402 tmp = (mfdcr (memcfgd) & ~0xFFE00000) | 0x80C00000;
403 mtdcr (memcfga, mem_mcopt1);
404 mtdcr (memcfgd, tmp);
411 int board_pre_init (void)
415 /*-------------------------------------------------------------------------+
416 | Interrupt controller setup for the PIP405 board.
417 | Note: IRQ 0-15 405GP internally generated; active high; level sensitive
418 | IRQ 16 405GP internally generated; active low; level sensitive
420 | IRQ 25 (EXT IRQ 0) SouthBridge; active low; level sensitive
421 | IRQ 26 (EXT IRQ 1) NMI: active low; level sensitive
422 | IRQ 27 (EXT IRQ 2) SMI: active Low; level sensitive
423 | IRQ 28 (EXT IRQ 3) PCI SLOT 3; active low; level sensitive
424 | IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
425 | IRQ 30 (EXT IRQ 5) PCI SLOT 1; active low; level sensitive
426 | IRQ 31 (EXT IRQ 6) PCI SLOT 0; active low; level sensitive
427 | Note for MIP405 board:
428 | An interrupt taken for the SouthBridge (IRQ 25) indicates that
429 | the Interrupt Controller in the South Bridge has caused the
430 | interrupt. The IC must be read to determine which device
431 | caused the interrupt.
433 +-------------------------------------------------------------------------*/
434 mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
435 mtdcr (uicer, 0x00000000); /* disable all ints */
436 mtdcr (uiccr, 0x00000000); /* set all to be non-critical (for now) */
437 mtdcr (uicpr, 0xFFFFFF80); /* set int polarities */
438 mtdcr (uictr, 0x10000000); /* set int trigger levels */
439 mtdcr (uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */
440 mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
446 * Get some PLD Registers
449 unsigned short get_pld_parvers (void)
451 unsigned short result;
454 rc = in8 (PLD_PART_REG);
455 result = (unsigned short) rc << 8;
456 rc = in8 (PLD_VERS_REG);
463 void user_led0 (unsigned char on)
466 out8 (PLD_COM_MODE_REG, (in8 (PLD_COM_MODE_REG) | 0x4));
468 out8 (PLD_COM_MODE_REG, (in8 (PLD_COM_MODE_REG) & 0xfb));
472 void ide_set_reset (int idereset)
474 /* if reset = 1 IDE reset will be asserted */
476 out8 (PLD_COM_MODE_REG, (in8 (PLD_COM_MODE_REG) | 0x1));
479 out8 (PLD_COM_MODE_REG, (in8 (PLD_COM_MODE_REG) & 0xfe));
484 /* ------------------------------------------------------------------------- */
487 * Check Board Identity:
490 int checkboard (void)
493 unsigned char bc, var, rc;
495 backup_t *b = (backup_t *) s;
499 bc = get_board_revcfg ();
503 for (i = 0; i < 4; i++) {
509 i = getenv_r ("serial#", s, 32);
510 if ((i == 0) || strncmp (s, "MIP405", 6)) {
511 get_backup_values (b);
512 if (strncmp (b->signature, "MPL\0", 4) != 0) {
513 puts ("### No HW ID - assuming MIP405");
514 printf ("-%d Rev %c", rc, 'A' + ((bc >> 4) & 0xf));
516 b->serial_name[6] = 0;
517 printf ("%s-%d Rev %c SN: %s", b->serial_name, rc,
518 'A' + ((bc >> 4) & 0xf), &b->serial_name[7]);
522 printf ("%s-%d Rev %c SN: %s", s, rc, 'A' + ((bc >> 4) & 0xf),
525 bc = in8 (PLD_EXT_CONF_REG);
526 printf (" Boot Config: 0x%x\n", bc);
531 /* ------------------------------------------------------------------------- */
532 /* ------------------------------------------------------------------------- */
534 initdram(int board_type) reads EEPROM via I2c. EEPROM contains all of
535 the necessary info for SDRAM controller configuration
537 /* ------------------------------------------------------------------------- */
538 /* ------------------------------------------------------------------------- */
539 static int test_dram (unsigned long ramsize);
541 long int initdram (int board_type)
544 unsigned long bank_reg[4], tmp, bank_size;
546 unsigned long TotalSize;
549 /* since the DRAM controller is allready set up, calculate the size with the
551 mtdcr (memcfga, mem_mb0cf);
552 bank_reg[0] = mfdcr (memcfgd);
553 mtdcr (memcfga, mem_mb1cf);
554 bank_reg[1] = mfdcr (memcfgd);
555 mtdcr (memcfga, mem_mb2cf);
556 bank_reg[2] = mfdcr (memcfgd);
557 mtdcr (memcfga, mem_mb3cf);
558 bank_reg[3] = mfdcr (memcfgd);
560 for (i = 0; i < 4; i++) {
561 if ((bank_reg[i] & 0x1) == 0x1) {
562 tmp = (bank_reg[i] >> 17) & 0x7;
563 bank_size = 4 << tmp;
564 TotalSize += bank_size;
568 mtdcr (memcfga, mem_ecccf);
569 tmp = mfdcr (memcfgd);
575 test_dram (TotalSize * MEGA_BYTE);
576 return (TotalSize * MEGA_BYTE);
579 /* ------------------------------------------------------------------------- */
581 extern int mem_test (unsigned long start, unsigned long ramsize,
584 static int test_dram (unsigned long ramsize)
587 mem_test (0L, ramsize, 1);
589 /* not yet implemented */
593 int misc_init_r (void)
599 void print_mip405_rev (void)
601 unsigned char part, vers, cfg, rev;
603 cfg = get_board_revcfg ();
606 rev = (((vers & 0x1) ? 0x8 : 0) |
607 ((vers & 0x2) ? 0x4 : 0) |
608 ((vers & 0x4) ? 0x2 : 0) | ((vers & 0x8) ? 0x1 : 0));
610 part = in8 (PLD_PART_REG);
611 vers = in8 (PLD_VERS_REG);
612 printf ("Rev: MIP405-%d Rev %c PLD%d Vers %d\n",
613 (16 - rev), ((cfg >> 4) & 0xf) + 'A', part, vers);
617 int last_stage_init (void)
619 if (miiphy_write (0x1, 0x14, 0x2402) != 0) {
620 printf ("Error writing to the PHY\n");
628 /***************************************************************************
629 * some helping routines
632 int overwrite_console (void)
634 return ((in8 (PLD_EXT_CONF_REG) & 0x1)==0); /* return TRUE if console should be overwritten */
638 /************************************************************************
640 ************************************************************************/
641 void print_mip405_info (void)
643 unsigned char part, vers, cfg, irq_reg, com_mode, ext;
645 part = in8 (PLD_PART_REG);
646 vers = in8 (PLD_VERS_REG);
647 cfg = in8 (PLD_BOARD_CFG_REG);
648 irq_reg = in8 (PLD_IRQ_REG);
649 com_mode = in8 (PLD_COM_MODE_REG);
650 ext = in8 (PLD_EXT_CONF_REG);
652 printf ("PLD Part %d version %d\n", part, vers);
653 printf ("Board Revision %c\n", ((cfg >> 4) & 0xf) + 'A');
654 printf ("Population Options %d %d %d %d\n", (cfg) & 0x1,
655 (cfg >> 1) & 0x1, (cfg >> 2) & 0x1, (cfg >> 3) & 0x1);
656 printf ("User LED %s\n", (com_mode & 0x4) ? "on" : "off");
657 printf ("UART Clocks %d\n", (com_mode >> 4) & 0x3);
658 printf ("Test ist %x\n", com_mode);
659 printf ("User Config Switch %d %d %d %d %d %d %d %d\n",
660 (ext) & 0x1, (ext >> 1) & 0x1, (ext >> 2) & 0x1,
661 (ext >> 3) & 0x1, (ext >> 4) & 0x1, (ext >> 5) & 0x1,
662 (ext >> 6) & 0x1, (ext >> 7) & 0x1);
663 printf ("SER1 uses handshakes %s\n",
664 (ext & 0x80) ? "DTR/DSR" : "RTS/CTS");
665 printf ("IDE Reset %s\n", (ext & 0x01) ? "asserted" : "not asserted");
667 printf (" PIIX INTR: %s\n", (irq_reg & 0x80) ? "inactive" : "active");
668 printf (" UART0 IRQ: %s\n", (irq_reg & 0x40) ? "inactive" : "active");
669 printf (" UART1 IRQ: %s\n", (irq_reg & 0x20) ? "inactive" : "active");
670 printf (" PIIX SMI: %s\n", (irq_reg & 0x10) ? "inactive" : "active");
671 printf (" PIIX INIT: %s\n", (irq_reg & 0x8) ? "inactive" : "active");
672 printf (" PIIX NMI: %s\n", (irq_reg & 0x4) ? "inactive" : "active");