1 /*------------------------------------------------------------------------------+
3 * This source code has been made available to you by IBM on an AS-IS
4 * basis. Anyone receiving this source is licensed under IBM
5 * copyrights to use it in any way he or she deems fit, including
6 * copying it, modifying it, compiling it, and redistributing it either
7 * with or without modifications. No license under IBM patents or
8 * patent applications is to be implied by the copyright license.
10 * Any user of this software should understand that IBM cannot provide
11 * technical support for this software and will not be responsible for
12 * any consequences resulting from the use of this software.
14 * Any person who transfers this source code or any derivative work
15 * must include the IBM copyright notice, this paragraph, and the
16 * preceding two paragraphs in the transferred software.
18 * COPYRIGHT I B M CORPORATION 1995
19 * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
20 *-------------------------------------------------------------------------------*/
22 /*-----------------------------------------------------------------------------
23 * Function: ext_bus_cntlr_init
24 * Description: Initializes the External Bus Controller for the external
25 * peripherals. IMPORTANT: For pass1 this code must run from
26 * cache since you can not reliably change a peripheral banks
27 * timing register (pbxap) while running code from that bank.
28 * For ex., since we are running from ROM on bank 0, we can NOT
29 * execute the code that modifies bank 0 timings from ROM, so
30 * we run it from cache.
31 * Bank 0 - Flash or Multi Purpose Socket
32 * Bank 1 - Multi Purpose Socket or Flash (set in C-Code)
33 * Bank 2 - UART 1 (set in C-Code)
34 * Bank 3 - UART 2 (set in C-Code)
38 * Bank 7 - PLD Register
39 *-----------------------------------------------------------------------------*/
42 #define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
44 #include <configs/MIP405.h>
45 #include <ppc_asm.tmpl>
48 #include <asm/cache.h>
53 .globl ext_bus_cntlr_init
55 mflr r4 /* save link register */
58 mflr r3 /* get address of ..getAddr */
59 mtlr r4 /* restore link register */
60 addi r4,0,14 /* set ctr to 14; used to prefetch */
61 mtctr r4 /* 14 cache lines to fit this function */
62 /* in cache (gives us 8x14=112 instrctns) */
64 icbt r0,r3 /* prefetch cache line for addr in r3 */
65 addi r3,r3,32 /* move to next cache line */
66 bdnz ..ebcloop /* continue for 14 cache lines */
68 /*-------------------------------------------------------------------
69 * Delay to ensure all accesses to ROM are complete before changing
71 *------------------------------------------------------------------- */
76 bdnz ..spinlp /* spin loop */
78 /*-----------------------------------------------------------------------
80 *----------------------------------------------------------------------- */
85 andi. r0, r4, 0x2000 /* mask out irrelevant bits */
86 beq 0f /* jump if 8 bit bus width */
88 /* setup 16 bit things (Flash Boot)
89 *-----------------------------------------------------------------------
90 * Memory Bank 0 (16 Bit Flash) initialization
91 *---------------------------------------------------------------------- */
95 /* addis r4,0,0xFF8F */
96 /* ori r4,r4,0xFE80 */
97 /* addis r4,0,0x9B01 */
98 /* ori r4,r4,0x5480 */
99 addis r4,0,(FLASH_AP_B)@h
100 ori r4,r4,(FLASH_AP_B)@l
105 /* BS=0x010(4MB),BU=0x3(R/W), */
106 /* addis r4,0,((FLASH_BASE0_PRELIM & 0xFFF00000) | 0x00050000)@h */
107 /* ori r4,r4,0xA000 / * BW=0x01(16 bits) */
108 addis r4,0,(FLASH_CR_B)@h
109 ori r4,r4,(FLASH_CR_B)@l
115 /* 8Bit boot mode: */
116 /*-----------------------------------------------------------------------
117 * Memory Bank 0 Multi Purpose Socket initialization
118 *----------------------------------------------------------------------- */
119 /* 0x7F8FFE80 slowest boot */
126 addis r4,0,(MPS_AP_B)@h
127 ori r4,r4,(MPS_AP_B)@l
133 /* BS=0x010(4MB),BU=0x3(R/W), */
134 /* addis r4,0,((FLASH_BASE0_PRELIM & 0xFFF00000) | 0x00050000)@h */
135 /* ori r4,r4,0x8000 / * BW=0x0( 8 bits) */
137 addis r4,0,(MPS_CR_B)@h
138 ori r4,r4,(MPS_CR_B)@l
144 /*-----------------------------------------------------------------------
145 * Memory Bank 2-3-4-5-6 (not used) initialization
146 *-----------------------------------------------------------------------*/
188 nop /* pass2 DCR errata #8 */
191 /*-----------------------------------------------------------------------------
192 * Function: sdram_init
193 * Description: Configures the internal SRAM memory. and setup the
194 * Stackpointer in it.
195 *----------------------------------------------------------------------------- */