2 * SPDX-License-Identifier: GPL-2.0 IBM-pibs
4 /*-----------------------------------------------------------------------------
5 * Function: ext_bus_cntlr_init
6 * Description: Initializes the External Bus Controller for the external
7 * peripherals. IMPORTANT: For pass1 this code must run from
8 * cache since you can not reliably change a peripheral banks
9 * timing register (pbxap) while running code from that bank.
10 * For ex., since we are running from ROM on bank 0, we can NOT
11 * execute the code that modifies bank 0 timings from ROM, so
12 * we run it from cache.
13 * Bank 0 - Flash or Multi Purpose Socket
14 * Bank 1 - Multi Purpose Socket or Flash (set in C-Code)
15 * Bank 2 - UART 1 (set in C-Code)
16 * Bank 3 - UART 2 (set in C-Code)
20 * Bank 7 - PLD Register
21 *-----------------------------------------------------------------------------*/
22 #define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
24 #include <configs/MIP405.h>
25 #include <ppc_asm.tmpl>
28 #include <asm/cache.h>
30 #include <asm/ppc4xx.h>
34 .globl ext_bus_cntlr_init
36 mflr r4 /* save link register */
37 mfdcr r3,CPC0_PSR /* get strapping reg */
38 andi. r0, r3, PSR_ROM_LOC /* mask out irrelevant bits */
39 bnelr /* jump back if PCI boot */
43 mflr r3 /* get address of ..getAddr */
44 mtlr r4 /* restore link register */
45 addi r4,0,14 /* set ctr to 14; used to prefetch */
46 mtctr r4 /* 14 cache lines to fit this function */
47 /* in cache (gives us 8x14=112 instrctns) */
49 icbt r0,r3 /* prefetch cache line for addr in r3 */
50 addi r3,r3,32 /* move to next cache line */
51 bdnz ..ebcloop /* continue for 14 cache lines */
53 /*-------------------------------------------------------------------
54 * Delay to ensure all accesses to ROM are complete before changing
56 *------------------------------------------------------------------- */
61 bdnz ..spinlp /* spin loop */
63 /*-----------------------------------------------------------------------
65 *----------------------------------------------------------------------- */
70 andi. r0, r4, 0x2000 /* mask out irrelevant bits */
71 beq 0f /* jump if 8 bit bus width */
73 /* setup 16 bit things
74 *-----------------------------------------------------------------------
75 * Memory Bank 0 (16 Bit Flash) initialization
76 *---------------------------------------------------------------------- */
80 addis r4,0,(FLASH_AP_B)@h
81 ori r4,r4,(FLASH_AP_B)@l
86 /* BS=0x010(4MB),BU=0x3(R/W), */
87 addis r4,0,(FLASH_CR_B)@h
88 ori r4,r4,(FLASH_CR_B)@l
95 /*-----------------------------------------------------------------------
96 * Memory Bank 0 Multi Purpose Socket initialization
97 *----------------------------------------------------------------------- */
98 /* 0x7F8FFE80 slowest boot */
100 mtdcr EBC0_CFGADDR,r4
101 addis r4,0,(MPS_AP_B)@h
102 ori r4,r4,(MPS_AP_B)@l
103 mtdcr EBC0_CFGDATA,r4
106 mtdcr EBC0_CFGADDR,r4
107 /* BS=0x010(4MB),BU=0x3(R/W), */
108 addis r4,0,(MPS_CR_B)@h
109 ori r4,r4,(MPS_CR_B)@l
111 mtdcr EBC0_CFGDATA,r4
115 /*-----------------------------------------------------------------------
116 * Memory Bank 2-3-4-5-6 (not used) initialization
117 *-----------------------------------------------------------------------*/
119 mtdcr EBC0_CFGADDR,r4
122 mtdcr EBC0_CFGDATA,r4
125 mtdcr EBC0_CFGADDR,r4
128 mtdcr EBC0_CFGDATA,r4
131 mtdcr EBC0_CFGADDR,r4
134 mtdcr EBC0_CFGDATA,r4
137 mtdcr EBC0_CFGADDR,r4
140 mtdcr EBC0_CFGDATA,r4
143 mtdcr EBC0_CFGADDR,r4
146 mtdcr EBC0_CFGDATA,r4
149 mtdcr EBC0_CFGADDR,r4
152 mtdcr EBC0_CFGDATA,r4
155 mtdcr EBC0_CFGADDR,r4
158 mtdcr EBC0_CFGDATA,r4
159 nop /* pass2 DCR errata #8 */
162 #if defined(CONFIG_BOOT_PCI)
163 .section .bootpg,"ax"
165 /*******************************************
169 /* first handle errata #68 / PCI_18 */
170 iccci r0, r0 /* invalidate I-cache */
172 mticcr r31 /* ICCR = 0 (all uncachable) */
175 mfccr0 r28 /* set CCR0[24] = 1 */
179 /* setup PMM0MA (0xEF400004) and PMM0PCIHA (0xEF40000C) */
181 addi r28, r28, 0x0004
182 stw r31, 0x0C(r28) /* clear PMM0PCIHA */
183 lis r29, 0xFFF8 /* open 512 kByte */
184 addi r29, r29, 0x0001/* and enable this region */
185 stwbrx r29, r0, r28 /* write PMM0MA */
187 lis r28, 0xEEC0 /* address of PCIC0_CFGADDR */
188 addi r29, r28, 4 /* add 4 to r29 -> PCIC0_CFGDATA */
190 lis r31, 0x8000 /* set en bit bus 0 */
191 ori r31, r31, 0x304C/* device 6 func 0 reg 4C (XBCS register) */
192 stwbrx r31, r0, r28 /* write it */
194 lwbrx r31, r0, r29 /* load XBCS register */
195 oris r31, r31, 0x02C4/* clear BIOSCS WPE, set lower, extended and 1M extended BIOS enable */
196 stwbrx r31, r0, r29 /* write back XBCS register */
200 b _start /* normal start */