3 * Denis Peter, MPL AG Switzerland
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * Note: Part of this code has been derived from linux
30 /* Command register */
32 #define USBCMD_RS 0x0001 /* Run/Stop */
33 #define USBCMD_HCRESET 0x0002 /* Host reset */
34 #define USBCMD_GRESET 0x0004 /* Global reset */
35 #define USBCMD_EGSM 0x0008 /* Global Suspend Mode */
36 #define USBCMD_FGR 0x0010 /* Force Global Resume */
37 #define USBCMD_SWDBG 0x0020 /* SW Debug mode */
38 #define USBCMD_CF 0x0040 /* Config Flag (sw only) */
39 #define USBCMD_MAXP 0x0080 /* Max Packet (0 = 32, 1 = 64) */
43 #define USBSTS_USBINT 0x0001 /* Interrupt due to IOC */
44 #define USBSTS_ERROR 0x0002 /* Interrupt due to error */
45 #define USBSTS_RD 0x0004 /* Resume Detect */
46 #define USBSTS_HSE 0x0008 /* Host System Error - basically PCI problems */
47 #define USBSTS_HCPE 0x0010 /* Host Controller Process Error - the scripts were buggy */
48 #define USBSTS_HCH 0x0020 /* HC Halted */
50 /* Interrupt enable register */
52 #define USBINTR_TIMEOUT 0x0001 /* Timeout/CRC error enable */
53 #define USBINTR_RESUME 0x0002 /* Resume interrupt enable */
54 #define USBINTR_IOC 0x0004 /* Interrupt On Complete enable */
55 #define USBINTR_SP 0x0008 /* Short packet interrupt enable */
58 #define USBFLBASEADD 8
61 /* USB port status and control registers */
64 #define USBPORTSC_CCS 0x0001 /* Current Connect Status ("device present") */
65 #define USBPORTSC_CSC 0x0002 /* Connect Status Change */
66 #define USBPORTSC_PE 0x0004 /* Port Enable */
67 #define USBPORTSC_PEC 0x0008 /* Port Enable Change */
68 #define USBPORTSC_LS 0x0030 /* Line Status */
69 #define USBPORTSC_RD 0x0040 /* Resume Detect */
70 #define USBPORTSC_LSDA 0x0100 /* Low Speed Device Attached */
71 #define USBPORTSC_PR 0x0200 /* Port Reset */
72 #define USBPORTSC_SUSP 0x1000 /* Suspend */
74 /* Legacy support register */
75 #define USBLEGSUP 0xc0
76 #define USBLEGSUP_DEFAULT 0x2000 /* only PIRQ enable set */
78 #define UHCI_NULL_DATA_SIZE 0x7ff /* for UHCI controller TD */
79 #define UHCI_PID 0xff /* PID MASK */
81 #define UHCI_PTR_BITS 0x000F
82 #define UHCI_PTR_TERM 0x0001
83 #define UHCI_PTR_QH 0x0002
84 #define UHCI_PTR_DEPTH 0x0004
86 /* for TD <status>: */
87 #define TD_CTRL_SPD (1 << 29) /* Short Packet Detect */
88 #define TD_CTRL_C_ERR_MASK (3 << 27) /* Error Counter bits */
89 #define TD_CTRL_LS (1 << 26) /* Low Speed Device */
90 #define TD_CTRL_IOS (1 << 25) /* Isochronous Select */
91 #define TD_CTRL_IOC (1 << 24) /* Interrupt on Complete */
92 #define TD_CTRL_ACTIVE (1 << 23) /* TD Active */
93 #define TD_CTRL_STALLED (1 << 22) /* TD Stalled */
94 #define TD_CTRL_DBUFERR (1 << 21) /* Data Buffer Error */
95 #define TD_CTRL_BABBLE (1 << 20) /* Babble Detected */
96 #define TD_CTRL_NAK (1 << 19) /* NAK Received */
97 #define TD_CTRL_CRCTIMEO (1 << 18) /* CRC/Time Out Error */
98 #define TD_CTRL_BITSTUFF (1 << 17) /* Bit Stuff Error */
99 #define TD_CTRL_ACTLEN_MASK 0x7ff /* actual length, encoded as n - 1 */
101 #define TD_CTRL_ANY_ERROR (TD_CTRL_STALLED | TD_CTRL_DBUFERR | \
102 TD_CTRL_BABBLE | TD_CTRL_CRCTIME | TD_CTRL_BITSTUFF)
104 #define TD_TOKEN_TOGGLE 19
106 /* ------------------------------------------------------------------------------------
108 ------------------------------------------------------------------------------------ */
109 /* destination of request */
110 #define RH_INTERFACE 0x01
111 #define RH_ENDPOINT 0x02
112 #define RH_OTHER 0x03
114 #define RH_CLASS 0x20
115 #define RH_VENDOR 0x40
117 /* Requests: bRequest << 8 | bmRequestType */
118 #define RH_GET_STATUS 0x0080
119 #define RH_CLEAR_FEATURE 0x0100
120 #define RH_SET_FEATURE 0x0300
121 #define RH_SET_ADDRESS 0x0500
122 #define RH_GET_DESCRIPTOR 0x0680
123 #define RH_SET_DESCRIPTOR 0x0700
124 #define RH_GET_CONFIGURATION 0x0880
125 #define RH_SET_CONFIGURATION 0x0900
126 #define RH_GET_STATE 0x0280
127 #define RH_GET_INTERFACE 0x0A80
128 #define RH_SET_INTERFACE 0x0B00
129 #define RH_SYNC_FRAME 0x0C80
130 /* Our Vendor Specific Request */
131 #define RH_SET_EP 0x2000
133 /* Hub port features */
134 #define RH_PORT_CONNECTION 0x00
135 #define RH_PORT_ENABLE 0x01
136 #define RH_PORT_SUSPEND 0x02
137 #define RH_PORT_OVER_CURRENT 0x03
138 #define RH_PORT_RESET 0x04
139 #define RH_PORT_POWER 0x08
140 #define RH_PORT_LOW_SPEED 0x09
141 #define RH_C_PORT_CONNECTION 0x10
142 #define RH_C_PORT_ENABLE 0x11
143 #define RH_C_PORT_SUSPEND 0x12
144 #define RH_C_PORT_OVER_CURRENT 0x13
145 #define RH_C_PORT_RESET 0x14
148 #define RH_C_HUB_LOCAL_POWER 0x00
149 #define RH_C_HUB_OVER_CURRENT 0x01
151 #define RH_DEVICE_REMOTE_WAKEUP 0x00
152 #define RH_ENDPOINT_STALL 0x01
154 /* Our Vendor Specific feature */
155 #define RH_REMOVE_EP 0x00
159 #define RH_REQ_ERR -1
163 /* Transfer descriptor structure */
165 unsigned long link; /* next td/qh (LE)*/
166 unsigned long status; /* status of the td */
167 unsigned long info; /* Max Lenght / Endpoint / device address and PID */
168 unsigned long buffer; /* pointer to data buffer (LE) */
169 unsigned long dev_ptr; /* pointer to the assigned device (BE) */
170 unsigned long res[3]; /* reserved (TDs must be 8Byte aligned) */
171 } uhci_td_t, *puhci_td_t;
173 /* Queue Header structure */
175 unsigned long head; /* Next QH (LE)*/
176 unsigned long element; /* Queue element pointer (LE) */
177 unsigned long res[5]; /* reserved */
178 unsigned long dev_ptr; /* if 0 no tds have been assigned to this qh */
179 } uhci_qh_t, *puhci_qh_t;
181 struct virt_root_hub {
182 int devnum; /* Address of Root Hub endpoint */
183 int numports; /* number of ports */
184 int c_p_r[8]; /* C_PORT_RESET */
188 #endif /* _USB_UHCI_H_ */