2 * Copyright 2006 Freescale Semiconductor
4 * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 #include <asm/cache.h>
35 * Per table 27, page 58 of MPC8641HPCN spec.
37 int set_px_sysclk(ulong sysclk)
39 u8 sysclk_s, sysclk_r, sysclk_v, vclkh, vclkl, sysclk_aux;
91 printf("Unsupported SYSCLK frequency.\n");
95 vclkh = (sysclk_s << 5) | sysclk_r ;
98 out8(PIXIS_BASE + PIXIS_VCLKH, vclkh);
99 out8(PIXIS_BASE + PIXIS_VCLKL, vclkl);
101 out8(PIXIS_BASE + PIXIS_AUX,sysclk_aux);
107 int set_px_mpxpll(ulong mpxpll)
124 printf("Unsupported MPXPLL ratio.\n");
128 tmp = in8(PIXIS_BASE + PIXIS_VSPEED1);
129 tmp = (tmp & 0xF0) | (val & 0x0F);
130 out8(PIXIS_BASE + PIXIS_VSPEED1, tmp);
136 int set_px_corepll(ulong corepll)
141 switch ((int)corepll) {
161 printf("Unsupported COREPLL ratio.\n");
165 tmp = in8(PIXIS_BASE + PIXIS_VSPEED0);
166 tmp = (tmp & 0xE0) | (val & 0x1F);
167 out8(PIXIS_BASE + PIXIS_VSPEED0, tmp);
173 void read_from_px_regs(int set)
176 u8 tmp = in8(PIXIS_BASE + PIXIS_VCFGEN0);
182 out8(PIXIS_BASE + PIXIS_VCFGEN0, tmp);
186 void read_from_px_regs_altbank(int set)
189 u8 tmp = in8(PIXIS_BASE + PIXIS_VCFGEN1);
195 out8(PIXIS_BASE + PIXIS_VCFGEN1, tmp);
199 void set_altbank(void)
203 tmp = in8(PIXIS_BASE + PIXIS_VBOOT);
206 out8(PIXIS_BASE + PIXIS_VBOOT, tmp);
214 tmp = in8(PIXIS_BASE + PIXIS_VCTL);
216 out8(PIXIS_BASE + PIXIS_VCTL, tmp);
218 tmp = in8(PIXIS_BASE + PIXIS_VCTL);
220 out8(PIXIS_BASE + PIXIS_VCTL, tmp);
224 void set_px_go_with_watchdog(void)
228 tmp = in8(PIXIS_BASE + PIXIS_VCTL);
230 out8(PIXIS_BASE + PIXIS_VCTL, tmp);
232 tmp = in8(PIXIS_BASE + PIXIS_VCTL);
234 out8(PIXIS_BASE + PIXIS_VCTL, tmp);
238 int disable_watchdog(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
242 tmp = in8(PIXIS_BASE + PIXIS_VCTL);
244 out8(PIXIS_BASE + PIXIS_VCTL, tmp);
246 /* setting VCTL[WDEN] to 0 to disable watch dog */
247 tmp = in8(PIXIS_BASE + PIXIS_VCTL);
249 out8(PIXIS_BASE + PIXIS_VCTL, tmp);
256 diswd, 1, 0, disable_watchdog,
257 "diswd - Disable watchdog timer \n",
263 * This function takes the non-integral cpu:mpx pll ratio
264 * and converts it to an integer that can be used to assign
265 * FPGA register values.
266 * input: strptr i.e. argv[2]
269 ulong strfractoint(uchar *strptr)
273 int intarr_len = 0, decarr_len = 0, no_dec = 0;
274 ulong intval = 0, decval = 0;
275 uchar intarr[3], decarr[3];
277 /* Assign the integer part to intarr[]
278 * If there is no decimal point i.e.
279 * if the ratio is an integral value
280 * simply create the intarr.
283 while (strptr[i] != 46) {
284 if (strptr[i] == 0) {
288 intarr[i] = strptr[i];
292 /* Assign length of integer part to intarr_len. */
297 /* Currently needed only for single digit corepll ratios */
302 i++; /* Skipping the decimal point */
303 while ((strptr[i] > 47) && (strptr[i] < 58)) {
304 decarr[j] = strptr[i];
313 for (i = 0; i < decarr_len; i++)
315 decval = simple_strtoul(decarr, NULL, 10);
318 intval = simple_strtoul(intarr, NULL, 10);
319 intval = intval * mulconst;
321 retval = intval + decval;