2 * Copyright 2004 Freescale Semiconductor.
4 * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
6 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 #include <asm/processor.h>
31 #include <asm/immap_86xx.h>
34 #if defined(CONFIG_OF_FLAT_TREE)
36 extern void ft_cpu_setup(void *blob, bd_t *bd);
41 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
42 extern void ddr_enable_ecc(unsigned int dram_size);
45 #if defined(CONFIG_SPD_EEPROM)
46 #include "spd_sdram.h"
49 void sdram_init(void);
50 long int fixed_sdram(void);
53 int board_early_init_f(void)
60 puts("Board: MPC8641HPCN\n");
64 volatile immap_t *immap = (immap_t *) CFG_CCSRBAR;
65 volatile ccsr_gur_t *gur = &immap->im_gur;
66 volatile ccsr_pex_t *pex1 = &immap->im_pex1;
68 uint devdisr = gur->devdisr;
69 uint io_sel = (gur->pordevsr & MPC86xx_PORDEVSR_IO_SEL) >> 16;
70 uint host1_agent = (gur->porbmsr & MPC86xx_PORBMSR_HA) >> 17;
71 uint pex1_agent = (host1_agent == 0) || (host1_agent == 1);
73 if ((io_sel == 2 || io_sel == 3 || io_sel == 5
74 || io_sel == 6 || io_sel == 7 || io_sel == 0xF)
75 && !(devdisr & MPC86xx_DEVDISR_PCIEX1)) {
76 debug("PCI-EXPRESS 1: %s \n", pex1_agent ? "Agent" : "Host");
77 debug("0x%08x=0x%08x ", &pex1->pme_msg_det, pex1->pme_msg_det);
78 if (pex1->pme_msg_det) {
79 pex1->pme_msg_det = 0xffffffff;
80 debug(" with errors. Clearing. Now 0x%08x",
85 puts("PCI-EXPRESS 1: Disabled\n");
89 puts("PCI-EXPRESS1: Disabled\n");
97 initdram(int board_type)
101 #if defined(CONFIG_SPD_EEPROM)
102 dram_size = spd_sdram();
104 dram_size = fixed_sdram();
107 #if defined(CFG_RAMBOOT)
112 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
114 * Initialize and enable DDR ECC.
116 ddr_enable_ecc(dram_size);
124 #if defined(CFG_DRAM_TEST)
128 uint *pstart = (uint *) CFG_MEMTEST_START;
129 uint *pend = (uint *) CFG_MEMTEST_END;
132 puts("SDRAM test phase 1:\n");
133 for (p = pstart; p < pend; p++)
136 for (p = pstart; p < pend; p++) {
137 if (*p != 0xaaaaaaaa) {
138 printf("SDRAM test fails at: %08x\n", (uint) p);
143 puts("SDRAM test phase 2:\n");
144 for (p = pstart; p < pend; p++)
147 for (p = pstart; p < pend; p++) {
148 if (*p != 0x55555555) {
149 printf("SDRAM test fails at: %08x\n", (uint) p);
154 puts("SDRAM test passed.\n");
160 #if !defined(CONFIG_SPD_EEPROM)
162 * Fixed sdram init -- doesn't use serial presence detect.
167 #if !defined(CFG_RAMBOOT)
168 volatile immap_t *immap = (immap_t *) CFG_IMMR;
169 volatile ccsr_ddr_t *ddr = &immap->im_ddr1;
171 ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
172 ddr->cs0_config = CFG_DDR_CS0_CONFIG;
173 ddr->ext_refrec = CFG_DDR_EXT_REFRESH;
174 ddr->timing_cfg_0 = CFG_DDR_TIMING_0;
175 ddr->timing_cfg_1 = CFG_DDR_TIMING_1;
176 ddr->timing_cfg_2 = CFG_DDR_TIMING_2;
177 ddr->sdram_mode_1 = CFG_DDR_MODE_1;
178 ddr->sdram_mode_2 = CFG_DDR_MODE_2;
179 ddr->sdram_interval = CFG_DDR_INTERVAL;
180 ddr->sdram_data_init = CFG_DDR_DATA_INIT;
181 ddr->sdram_clk_cntl = CFG_DDR_CLK_CTRL;
182 ddr->sdram_ocd_cntl = CFG_DDR_OCD_CTRL;
183 ddr->sdram_ocd_status = CFG_DDR_OCD_STATUS;
185 #if defined (CONFIG_DDR_ECC)
186 ddr->err_disable = 0x0000008D;
187 ddr->err_sbe = 0x00ff0000;
193 #if defined (CONFIG_DDR_ECC)
194 /* Enable ECC checking */
195 ddr->sdram_cfg_1 = (CFG_DDR_CONTROL | 0x20000000);
197 ddr->sdram_cfg_1 = CFG_DDR_CONTROL;
198 ddr->sdram_cfg_2 = CFG_DDR_CONTROL2;
204 return CFG_SDRAM_SIZE * 1024 * 1024;
206 #endif /* !defined(CONFIG_SPD_EEPROM) */
209 #if defined(CONFIG_PCI)
211 * Initialize PCI Devices, report devices found.
214 #ifndef CONFIG_PCI_PNP
215 static struct pci_config_table pci_fsl86xxads_config_table[] = {
216 {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
217 PCI_IDSEL_NUMBER, PCI_ANY_ID,
218 pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
220 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER}},
226 static struct pci_controller hose = {
227 #ifndef CONFIG_PCI_PNP
228 config_table:pci_mpc86xxcts_config_table,
232 #endif /* CONFIG_PCI */
234 void pci_init_board(void)
237 extern void pci_mpc86xx_init(struct pci_controller *hose);
239 pci_mpc86xx_init(&hose);
240 #endif /* CONFIG_PCI */
243 #if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
245 ft_board_setup(void *blob, bd_t *bd)
250 ft_cpu_setup(blob, bd);
252 p = ft_get_prop(blob, "/memory/reg", &len);
254 *p++ = cpu_to_be32(bd->bi_memstart);
255 *p = cpu_to_be32(bd->bi_memsize);
262 mpc8641_reset_board(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
269 * No args is a simple reset request.
272 out8(PIXIS_BASE + PIXIS_RST, 0);
278 case 'f': /* reset with frequency changed */
281 read_from_px_regs(0);
283 val = set_px_sysclk(simple_strtoul(argv[2], NULL, 10));
285 corepll = strfractoint(argv[3]);
286 val = val + set_px_corepll(corepll);
287 val = val + set_px_mpxpll(simple_strtoul(argv[4], NULL, 10));
289 puts("Setting registers VCFGEN0 and VCTL\n");
290 read_from_px_regs(1);
291 puts("Resetting board with values from VSPEED0, VSPEED1, VCLKH, and VCLKL ....\n");
296 while (1) ; /* Not reached */
299 if (argv[2][1] == 'f') {
300 read_from_px_regs(0);
301 read_from_px_regs_altbank(0);
302 /* reset with frequency changed */
303 val = set_px_sysclk(simple_strtoul(argv[3], NULL, 10));
305 corepll = strfractoint(argv[4]);
306 val = val + set_px_corepll(corepll);
307 val = val + set_px_mpxpll(simple_strtoul(argv[5],
310 puts("Setting registers VCFGEN0, VCFGEN1, VBOOT, and VCTL\n");
312 read_from_px_regs(1);
313 read_from_px_regs_altbank(1);
314 puts("Enabling watchdog timer on the FPGA and resetting board with values from VSPEED0, VSPEED1, VCLKH, and VCLKL to boot from the other bank ....\n");
315 set_px_go_with_watchdog();
319 while (1) ; /* Not reached */
321 } else if (argv[2][1] == 'd') {
323 * Reset from alternate bank without changing
324 * frequencies but with watchdog timer enabled.
326 read_from_px_regs(0);
327 read_from_px_regs_altbank(0);
328 puts("Setting registers VCFGEN1, VBOOT, and VCTL\n");
330 read_from_px_regs_altbank(1);
331 puts("Enabling watchdog timer on the FPGA and resetting board to boot from the other bank....\n");
332 set_px_go_with_watchdog();
333 while (1) ; /* Not reached */
337 * Reset from next bank without changing
338 * frequency and without watchdog timer enabled.
340 read_from_px_regs(0);
341 read_from_px_regs_altbank(0);
344 puts("Setting registers VCFGNE1, VBOOT, and VCTL\n");
346 read_from_px_regs_altbank(1);
347 puts("Resetting board to boot from the other bank....\n");
356 puts("\nUsage: reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>\n");
357 puts(" reset altbank [cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>]\n");
358 puts(" reset altbank [wd]\n");
359 puts("For example: reset cf 40 2.5 10\n");
360 puts("See MPC8641HPCN Design Workbook for valid values of command line parameters.\n");
366 * Reads the FPGA on board for CONFIG_SYS_CLK_FREQ
370 get_board_sys_clk(ulong dummy)
372 u8 i, go_bit, rd_clks;
375 go_bit = in8(PIXIS_BASE + PIXIS_VCTL);
378 rd_clks = in8(PIXIS_BASE + PIXIS_VCFGEN0);
382 * Only if both go bit and the SCLK bit in VCFGEN0 are set
383 * should we be using the AUX register. Remember, we also set the
384 * GO bit to boot from the alternate bank on the on-board flash
389 i = in8(PIXIS_BASE + PIXIS_AUX);
391 i = in8(PIXIS_BASE + PIXIS_SPD);
393 i = in8(PIXIS_BASE + PIXIS_SPD);