2 * Copyright 2006, 2007 Freescale Semiconductor.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include <asm/processor.h>
26 #include <asm/immap_86xx.h>
30 #if defined(CONFIG_OF_FLAT_TREE)
32 extern void ft_cpu_setup(void *blob, bd_t *bd);
35 #include "../freescale/common/pixis.h"
37 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
38 extern void ddr_enable_ecc(unsigned int dram_size);
41 #if defined(CONFIG_SPD_EEPROM)
42 #include "spd_sdram.h"
45 void sdram_init(void);
46 long int fixed_sdram(void);
49 int board_early_init_f(void)
56 puts("Board: MPC8641HPCN\n");
60 volatile immap_t *immap = (immap_t *) CFG_CCSRBAR;
61 volatile ccsr_gur_t *gur = &immap->im_gur;
62 volatile ccsr_pex_t *pex1 = &immap->im_pex1;
64 uint devdisr = gur->devdisr;
65 uint io_sel = (gur->pordevsr & MPC86xx_PORDEVSR_IO_SEL) >> 16;
66 uint host1_agent = (gur->porbmsr & MPC86xx_PORBMSR_HA) >> 17;
67 uint pex1_agent = (host1_agent == 0) || (host1_agent == 1);
69 if ((io_sel == 2 || io_sel == 3 || io_sel == 5
70 || io_sel == 6 || io_sel == 7 || io_sel == 0xF)
71 && !(devdisr & MPC86xx_DEVDISR_PCIEX1)) {
72 debug("PCI-EXPRESS 1: %s \n", pex1_agent ? "Agent" : "Host");
73 debug("0x%08x=0x%08x ", &pex1->pme_msg_det, pex1->pme_msg_det);
74 if (pex1->pme_msg_det) {
75 pex1->pme_msg_det = 0xffffffff;
76 debug(" with errors. Clearing. Now 0x%08x",
81 puts("PCI-EXPRESS 1: Disabled\n");
85 puts("PCI-EXPRESS1: Disabled\n");
93 initdram(int board_type)
97 #if defined(CONFIG_SPD_EEPROM)
98 dram_size = spd_sdram();
100 dram_size = fixed_sdram();
103 #if defined(CFG_RAMBOOT)
108 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
110 * Initialize and enable DDR ECC.
112 ddr_enable_ecc(dram_size);
120 #if defined(CFG_DRAM_TEST)
124 uint *pstart = (uint *) CFG_MEMTEST_START;
125 uint *pend = (uint *) CFG_MEMTEST_END;
128 puts("SDRAM test phase 1:\n");
129 for (p = pstart; p < pend; p++)
132 for (p = pstart; p < pend; p++) {
133 if (*p != 0xaaaaaaaa) {
134 printf("SDRAM test fails at: %08x\n", (uint) p);
139 puts("SDRAM test phase 2:\n");
140 for (p = pstart; p < pend; p++)
143 for (p = pstart; p < pend; p++) {
144 if (*p != 0x55555555) {
145 printf("SDRAM test fails at: %08x\n", (uint) p);
150 puts("SDRAM test passed.\n");
156 #if !defined(CONFIG_SPD_EEPROM)
158 * Fixed sdram init -- doesn't use serial presence detect.
163 #if !defined(CFG_RAMBOOT)
164 volatile immap_t *immap = (immap_t *) CFG_IMMR;
165 volatile ccsr_ddr_t *ddr = &immap->im_ddr1;
167 ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
168 ddr->cs0_config = CFG_DDR_CS0_CONFIG;
169 ddr->ext_refrec = CFG_DDR_EXT_REFRESH;
170 ddr->timing_cfg_0 = CFG_DDR_TIMING_0;
171 ddr->timing_cfg_1 = CFG_DDR_TIMING_1;
172 ddr->timing_cfg_2 = CFG_DDR_TIMING_2;
173 ddr->sdram_mode_1 = CFG_DDR_MODE_1;
174 ddr->sdram_mode_2 = CFG_DDR_MODE_2;
175 ddr->sdram_interval = CFG_DDR_INTERVAL;
176 ddr->sdram_data_init = CFG_DDR_DATA_INIT;
177 ddr->sdram_clk_cntl = CFG_DDR_CLK_CTRL;
178 ddr->sdram_ocd_cntl = CFG_DDR_OCD_CTRL;
179 ddr->sdram_ocd_status = CFG_DDR_OCD_STATUS;
181 #if defined (CONFIG_DDR_ECC)
182 ddr->err_disable = 0x0000008D;
183 ddr->err_sbe = 0x00ff0000;
189 #if defined (CONFIG_DDR_ECC)
190 /* Enable ECC checking */
191 ddr->sdram_cfg_1 = (CFG_DDR_CONTROL | 0x20000000);
193 ddr->sdram_cfg_1 = CFG_DDR_CONTROL;
194 ddr->sdram_cfg_2 = CFG_DDR_CONTROL2;
200 return CFG_SDRAM_SIZE * 1024 * 1024;
202 #endif /* !defined(CONFIG_SPD_EEPROM) */
205 #if defined(CONFIG_PCI)
207 * Initialize PCI Devices, report devices found.
210 #ifndef CONFIG_PCI_PNP
211 static struct pci_config_table pci_fsl86xxads_config_table[] = {
212 {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
213 PCI_IDSEL_NUMBER, PCI_ANY_ID,
214 pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
216 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER}},
222 static struct pci_controller hose = {
223 #ifndef CONFIG_PCI_PNP
224 config_table:pci_mpc86xxcts_config_table,
228 #endif /* CONFIG_PCI */
230 void pci_init_board(void)
233 extern void pci_mpc86xx_init(struct pci_controller *hose);
235 pci_mpc86xx_init(&hose);
236 #endif /* CONFIG_PCI */
239 #if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
241 ft_board_setup(void *blob, bd_t *bd)
246 ft_cpu_setup(blob, bd);
248 p = ft_get_prop(blob, "/memory/reg", &len);
250 *p++ = cpu_to_be32(bd->bi_memstart);
251 *p = cpu_to_be32(bd->bi_memsize);
259 * Reads the FPGA on board for CONFIG_SYS_CLK_FREQ
263 get_board_sys_clk(ulong dummy)
265 u8 i, go_bit, rd_clks;
268 go_bit = in8(PIXIS_BASE + PIXIS_VCTL);
271 rd_clks = in8(PIXIS_BASE + PIXIS_VCFGEN0);
275 * Only if both go bit and the SCLK bit in VCFGEN0 are set
276 * should we be using the AUX register. Remember, we also set the
277 * GO bit to boot from the alternate bank on the on-board flash
282 i = in8(PIXIS_BASE + PIXIS_AUX);
284 i = in8(PIXIS_BASE + PIXIS_SPD);
286 i = in8(PIXIS_BASE + PIXIS_SPD);