2 * Copyright 2007 Freescale Semiconductor.
4 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 #include <asm/processor.h>
28 #include <asm/immap_85xx.h>
34 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
35 extern void ddr_enable_ecc(unsigned int dram_size);
38 extern long int spd_sdram(void);
40 void local_bus_init(void);
41 void sdram_init(void);
43 int board_early_init_f (void)
46 * Initialize local bus.
50 enable_8568mds_duart();
51 enable_8568mds_flash_write();
58 printf ("Board: 8568 MDS\n");
64 initdram(int board_type)
67 volatile immap_t *immap = (immap_t *)CFG_IMMR;
69 puts("Initializing\n");
71 #if defined(CONFIG_DDR_DLL)
74 * Work around to stabilize DDR DLL MSYNC_IN.
75 * Errata DDR9 seems to have been fixed.
76 * This is now the workaround for Errata DDR11:
77 * Override DLL = 1, Course Adj = 1, Tap Select = 0
80 volatile ccsr_gur_t *gur= &immap->im_gur;
82 gur->ddrdllcr = 0x81000000;
83 asm("sync;isync;msync");
87 dram_size = spd_sdram();
89 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
91 * Initialize and enable DDR ECC.
93 ddr_enable_ecc(dram_size);
96 * SDRAM Initialization
105 * Initialize Local Bus
110 volatile immap_t *immap = (immap_t *)CFG_IMMR;
111 volatile ccsr_gur_t *gur = &immap->im_gur;
112 volatile ccsr_lbc_t *lbc = &immap->im_lbc;
118 get_sys_info(&sysinfo);
119 clkdiv = (lbc->lcrr & 0x0f) * 2;
120 lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
122 gur->lbiuiplldcr1 = 0x00078080;
124 gur->lbiuiplldcr0 = 0x7c0f1bf0;
125 } else if (clkdiv == 8) {
126 gur->lbiuiplldcr0 = 0x6c0f1bf0;
127 } else if (clkdiv == 4) {
128 gur->lbiuiplldcr0 = 0x5c0f1bf0;
131 lbc->lcrr |= 0x00030000;
133 asm("sync;isync;msync");
137 * Initialize SDRAM memory on the Local Bus.
142 #if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM)
145 volatile immap_t *immap = (immap_t *)CFG_IMMR;
146 volatile ccsr_lbc_t *lbc = &immap->im_lbc;
147 uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
152 print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
155 * Setup SDRAM Base and Option Registers
157 lbc->or2 = CFG_OR2_PRELIM;
160 lbc->br2 = CFG_BR2_PRELIM;
163 lbc->lbcr = CFG_LBC_LBCR;
167 lbc->lsrt = CFG_LBC_LSRT;
168 lbc->mrtpr = CFG_LBC_MRTPR;
172 * MPC8568 uses "new" 15-16 style addressing.
174 lsdmr_common = CFG_LBC_LSDMR_COMMON;
175 lsdmr_common |= CFG_LBC_LSDMR_BSMA1516;
178 * Issue PRECHARGE ALL command.
180 lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_PCHALL;
183 ppcDcbf((unsigned long) sdram_addr);
187 * Issue 8 AUTO REFRESH commands.
189 for (idx = 0; idx < 8; idx++) {
190 lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_ARFRSH;
193 ppcDcbf((unsigned long) sdram_addr);
198 * Issue 8 MODE-set command.
200 lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_MRW;
203 ppcDcbf((unsigned long) sdram_addr);
207 * Issue NORMAL OP command.
209 lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_NORMAL;
212 ppcDcbf((unsigned long) sdram_addr);
213 udelay(200); /* Overkill. Must wait > 200 bus cycles */
215 #endif /* enable SDRAM init */
218 #if defined(CFG_DRAM_TEST)
222 uint *pstart = (uint *) CFG_MEMTEST_START;
223 uint *pend = (uint *) CFG_MEMTEST_END;
226 printf("Testing DRAM from 0x%08x to 0x%08x\n",
230 printf("DRAM test phase 1:\n");
231 for (p = pstart; p < pend; p++)
234 for (p = pstart; p < pend; p++) {
235 if (*p != 0xaaaaaaaa) {
236 printf ("DRAM test fails at: %08x\n", (uint) p);
241 printf("DRAM test phase 2:\n");
242 for (p = pstart; p < pend; p++)
245 for (p = pstart; p < pend; p++) {
246 if (*p != 0x55555555) {
247 printf ("DRAM test fails at: %08x\n", (uint) p);
252 printf("DRAM test passed.\n");
257 #if defined(CONFIG_PCI)
258 #ifndef CONFIG_PCI_PNP
259 static struct pci_config_table pci_mpc8568mds_config_table[] = {
261 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
262 pci_cfgfunc_config_device,
265 PCI_COMMON_MEMORY | PCI_COMMAND_MASTER}
271 static struct pci_controller hose[] = {
272 #ifndef CONFIG_PCI_PNP
273 { config_table: pci_mpc8568mds_config_table,},
275 #ifdef CONFIG_MPC85XX_PCI2
280 #endif /* CONFIG_PCI */
286 pci_mpc85xx_init(&hose);