2 * Copyright 2004 Freescale Semiconductor.
3 * Copyright (C) 2002,2003, Motorola Inc.
4 * Xianghua Xiao <X.Xiao@motorola.com>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include <ppc_asm.tmpl>
27 #include <asm/cache.h>
34 * TLB0 and TLB1 Entries
36 * Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR.
37 * However, CCSRBAR is then relocated to CFG_CCSRBAR right after
38 * these TLB entries are established.
40 * The TLB entries for DDR are dynamically setup in spd_sdram()
41 * and use TLB1 Entries 8 through 15 as needed according to the
44 * MAS0: tlbsel, esel, nv
45 * MAS1: valid, iprot, tid, ts, tsize
46 * MAS2: epn, sharen, x0, x1, w, i, m, g, e
47 * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr
60 .section .bootpg, "ax"
66 * Number of TLB0 and TLB1 entries in the following table
70 #if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
72 * TLB0 4K Non-cacheable, guarded
73 * 0xff700000 4K Initial CCSRBAR mapping
75 * This ends up at a TLB0 Index==0 entry, and must not collide
76 * with other TLB0 Entries.
78 .long TLB1_MAS0(0, 0, 0)
79 .long TLB1_MAS1(1, 0, 0, 0, 0)
80 .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,1,0,1,0)
81 .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,0,1,0,1,0,1)
83 #error("Update the number of table entries in tlb1_entry")
87 * TLB0 16K Cacheable, non-guarded
88 * 0xd001_0000 16K Temporary Global data for initialization
90 * Use four 4K TLB0 entries. These entries must be cacheable
91 * as they provide the bootstrap memory before the memory
92 * controler and real memory have been configured.
94 * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c,
95 * and must not collide with other TLB0 entries.
97 .long TLB1_MAS0(0, 0, 0)
98 .long TLB1_MAS1(1, 0, 0, 0, 0)
99 .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR),
101 .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR),
104 .long TLB1_MAS0(0, 0, 0)
105 .long TLB1_MAS1(1, 0, 0, 0, 0)
106 .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 * 1024),
108 .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 * 1024),
111 .long TLB1_MAS0(0, 0, 0)
112 .long TLB1_MAS1(1, 0, 0, 0, 0)
113 .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024),
115 .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 8 * 1024),
118 .long TLB1_MAS0(0, 0, 0)
119 .long TLB1_MAS1(1, 0, 0, 0, 0)
120 .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 * 1024),
122 .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 * 1024),
127 * TLB 0: 16M Non-cacheable, guarded
128 * 0xff000000 16M FLASH
129 * Out of reset this entry is only 4K.
131 .long TLB1_MAS0(1, 0, 0)
132 .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)
133 .long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE), 0,0,0,0,1,0,1,0)
134 .long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE), 0,0,0,0,0,1,0,1,0,1)
137 * TLB 1: 256M Non-cacheable, guarded
138 * 0x80000000 256M PCI1 MEM First half
140 .long TLB1_MAS0(1, 1, 0)
141 .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
142 .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE), 0,0,0,0,1,0,1,0)
143 .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
146 * TLB 2: 256M Non-cacheable, guarded
147 * 0x90000000 256M PCI1 MEM Second half
149 .long TLB1_MAS0(1, 2, 0)
150 .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
151 .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE + 0x10000000),
153 .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE + 0x10000000),
157 * TLB 3: 256M Non-cacheable, guarded
158 * 0xc0000000 256M Rapid IO MEM First half
160 .long TLB1_MAS0(1, 3, 0)
161 .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
162 .long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_BASE), 0,0,0,0,1,0,1,0)
163 .long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
166 * TLB 4: 256M Non-cacheable, guarded
167 * 0xd0000000 256M Rapid IO MEM Second half
169 .long TLB1_MAS0(1, 4, 0)
170 .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
171 .long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_BASE + 0x10000000),
173 .long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_BASE + 0x10000000),
177 * TLB 5: 64M Non-cacheable, guarded
178 * 0xe000_0000 1M CCSRBAR
179 * 0xe200_0000 16M PCI1 IO
181 .long TLB1_MAS0(1, 5, 0)
182 .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
183 .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), 0,0,0,0,1,0,1,0)
184 .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), 0,0,0,0,0,1,0,1,0,1)
187 * TLB 6: 64M Cacheable, non-guarded
188 * 0xf000_0000 64M LBC SDRAM
190 .long TLB1_MAS0(1, 6, 0)
191 .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
192 .long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,0,0,0)
193 .long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1)
196 * TLB 7: 16K Non-cacheable, guarded
197 * 0xf8000000 16K BCSR registers
199 .long TLB1_MAS0(1, 7, 0)
200 .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16K)
201 .long TLB1_MAS2(E500_TLB_EPN(CFG_BCSR), 0,0,0,0,1,0,1,0)
202 .long TLB1_MAS3(E500_TLB_RPN(CFG_BCSR), 0,0,0,0,0,1,0,1,0,1)
204 #if !defined(CONFIG_SPD_EEPROM)
207 * 0x00000000 64M DDR System memory
208 * 0x04000000 64M DDR System memory
209 * Without SPD EEPROM configured DDR, this must be setup manually.
210 * Make sure the TLB count at the top of this table is correct.
211 * Likely it needs to be increased by two for these entries.
213 #error("Update the number of table entries in tlb1_entry")
214 .long TLB1_MAS0(1, 8, 0)
215 .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
216 .long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,0,0,0,0)
217 .long TLB1_MAS3(E500_TLB_RPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1)
219 .long TLB1_MAS0(1, 9, 0)
220 .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
221 .long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE + 0x4000000),
223 .long TLB1_MAS3(E500_TLB_RPN(CFG_DDR_SDRAM_BASE + 0x4000000),
230 * LAW(Local Access Window) configuration:
232 * 0x0000_0000 0x7fff_ffff DDR 2G
233 * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
234 * 0xc000_0000 0xdfff_ffff RapidIO 512M
235 * 0xe000_0000 0xe000_ffff CCSR 1M
236 * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M
237 * 0xf000_0000 0xf7ff_ffff SDRAM 128M
238 * 0xf800_0000 0xf80f_ffff BCSR 1M
239 * 0xff00_0000 0xffff_ffff FLASH (boot bank) 16M
242 * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
243 * If flash is 8M at default position (last 8M), no LAW needed.
246 #if !defined(CONFIG_SPD_EEPROM)
247 #define LAWBAR0 ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff)
248 #define LAWAR0 (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M))
251 #define LAWAR0 ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN)
254 #define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff)
255 #define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_512M))
258 * This is not so much the SDRAM map as it is the whole localbus map.
260 #define LAWBAR2 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff)
261 #define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M))
263 #define LAWBAR3 ((CFG_PCI1_IO_PHYS>>12) & 0xfffff)
264 #define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_1M))
267 * Rapid IO at 0xc000_0000 for 512 M
269 #define LAWBAR4 ((CFG_RIO_MEM_BASE>>12) & 0xfffff)
270 #define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M))
273 .section .bootpg, "ax"
278 .long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2,LAWBAR3,LAWAR3