2 * (C) Copyright 2002,2003, Motorola Inc.
3 * Xianghua Xiao, (X.Xiao@motorola.com)
5 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 #include <asm/processor.h>
29 #include <asm/immap_85xx.h>
30 #include <asm/fsl_ddr_sdram.h>
31 #include <spd_sdram.h>
33 long int fixed_sdram (void);
35 int board_pre_init (void)
37 #if defined(CONFIG_PCI)
38 volatile ccsr_pcix_t *pci = (void *)(CFG_MPC85xx_PCIX_ADDR);
40 pci->peer &= 0xffffffdf; /* disable master abort */
49 get_sys_info (&sysinfo);
51 printf ("Board: Freescale MPC8540EVAL Board\n");
52 printf ("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000);
53 printf ("\tCCB: %lu MHz\n", sysinfo.freqSystemBus / 1000000);
54 printf ("\tDDR: %lu MHz\n", sysinfo.freqSystemBus / 2000000);
55 if((CFG_LBC_LCRR & 0x0f) == 2 || (CFG_LBC_LCRR & 0x0f) == 4 \
56 || (CFG_LBC_LCRR & 0x0f) == 8) {
57 printf ("\tLBC: %lu MHz\n",
58 sysinfo.freqSystemBus / 1000000/(CFG_LBC_LCRR & 0x0f));
60 printf("\tLBC: unknown\n");
62 printf("L1 D-cache 32KB, L1 I-cache 32KB enabled.\n");
66 phys_size_t initdram (int board_type)
70 #if !defined(CONFIG_RAM_AS_FLASH)
71 volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
75 #if !defined(CONFIG_RAM_AS_FLASH) || defined(CONFIG_DDR_DLL)
76 volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
79 #if defined(CONFIG_DDR_DLL)
82 /* Work around to stabilize DDR DLL */
83 temp_ddrdll = gur->ddrdllcr;
84 gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000;
85 asm("sync;isync;msync");
88 #if defined(CONFIG_SPD_EEPROM)
89 dram_size = fsl_ddr_sdram();
90 dram_size = setup_ddr_tlbs(dram_size / 0x100000);
91 dram_size *= 0x100000;
93 dram_size = fixed_sdram ();
96 #if defined(CFG_RAMBOOT)
100 #if !defined(CONFIG_RAM_AS_FLASH) /* LocalBus is not emulating flash */
101 get_sys_info(&sysinfo);
102 /* if localbus freq is less than 66Mhz,we use bypass mode,otherwise use DLL */
103 if(sysinfo.freqSystemBus/(CFG_LBC_LCRR & 0x0f) < 66000000) {
104 lbc->lcrr = (CFG_LBC_LCRR & 0x0fffffff)| 0x80000000;
106 lbc->lcrr = CFG_LBC_LCRR & 0x7fffffff;
108 temp_lbcdll = gur->lbcdllcr;
109 gur->lbcdllcr = ((temp_lbcdll & 0xff) << 16 ) | 0x80000000;
110 asm("sync;isync;msync");
112 lbc->or2 = CFG_OR2_PRELIM; /* 64MB SDRAM */
113 lbc->br2 = CFG_BR2_PRELIM;
114 lbc->lbcr = CFG_LBC_LBCR;
115 lbc->lsdmr = CFG_LBC_LSDMR_1;
117 * (ulong *)0 = 0x000000ff;
118 lbc->lsdmr = CFG_LBC_LSDMR_2;
120 * (ulong *)0 = 0x000000ff;
121 lbc->lsdmr = CFG_LBC_LSDMR_3;
123 * (ulong *)0 = 0x000000ff;
124 lbc->lsdmr = CFG_LBC_LSDMR_4;
126 * (ulong *)0 = 0x000000ff;
127 lbc->lsdmr = CFG_LBC_LSDMR_5;
129 lbc->lsrt = CFG_LBC_LSRT;
131 lbc->mrtpr = CFG_LBC_MRTPR;
135 #if defined(CONFIG_DDR_ECC)
137 /* Initialize all of memory for ECC, then
141 volatile ccsr_ddr_t *ddr= (void *)(CFG_MPC85xx_DDR_ADDR);
143 for (*p = 0; p < (uint *)(8 * 1024); p++) {
144 if (((unsigned int)p & 0x1f) == 0) { dcbz(p); }
145 *p = (unsigned int)0xdeadbeef;
146 if (((unsigned int)p & 0x1c) == 0x1c) { dcbf(p); }
150 dma_xfer((uint *)0x2000,0x2000,(uint *)0);
152 dma_xfer((uint *)0x4000,0x4000,(uint *)0);
154 dma_xfer((uint *)0x8000,0x8000,(uint *)0);
156 dma_xfer((uint *)0x10000,0x10000,(uint *)0);
158 dma_xfer((uint *)0x20000,0x20000,(uint *)0);
160 dma_xfer((uint *)0x40000,0x40000,(uint *)0);
162 dma_xfer((uint *)0x80000,0x80000,(uint *)0);
164 dma_xfer((uint *)0x100000,0x100000,(uint *)0);
166 dma_xfer((uint *)0x200000,0x200000,(uint *)0);
168 dma_xfer((uint *)0x400000,0x400000,(uint *)0);
170 for (i = 1; i < dram_size / 0x800000; i++) {
171 dma_xfer((uint *)(0x800000*i),0x800000,(uint *)0);
174 /* Enable errors for ECC */
175 ddr->err_disable = 0x00000000;
176 asm("sync;isync;msync");
183 #if defined(CFG_DRAM_TEST)
186 uint *pstart = (uint *) CFG_MEMTEST_START;
187 uint *pend = (uint *) CFG_MEMTEST_END;
190 printf("SDRAM test phase 1:\n");
191 for (p = pstart; p < pend; p++)
194 for (p = pstart; p < pend; p++) {
195 if (*p != 0xaaaaaaaa) {
196 printf ("SDRAM test fails at: %08x\n", (uint) p);
201 printf("SDRAM test phase 2:\n");
202 for (p = pstart; p < pend; p++)
205 for (p = pstart; p < pend; p++) {
206 if (*p != 0x55555555) {
207 printf ("SDRAM test fails at: %08x\n", (uint) p);
212 printf("SDRAM test passed.\n");
217 #if !defined(CONFIG_SPD_EEPROM)
218 /*************************************************************************
219 * fixed sdram init -- doesn't use serial presence detect.
220 ************************************************************************/
221 long int fixed_sdram (void)
224 volatile ccsr_ddr_t *ddr= (void *)(CFG_MPC85xx_DDR_ADDR);
226 ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
227 ddr->cs0_config = CFG_DDR_CS0_CONFIG;
228 ddr->timing_cfg_1 = CFG_DDR_TIMING_1;
229 ddr->timing_cfg_2 = CFG_DDR_TIMING_2;
230 ddr->sdram_mode = CFG_DDR_MODE;
231 ddr->sdram_interval = CFG_DDR_INTERVAL;
232 #if defined (CONFIG_DDR_ECC)
233 ddr->err_disable = 0x0000000D;
234 ddr->err_sbe = 0x00ff0000;
236 asm("sync;isync;msync");
238 #if defined (CONFIG_DDR_ECC)
239 /* Enable ECC checking */
240 ddr->sdram_cfg = (CFG_DDR_CONTROL | 0x20000000);
242 ddr->sdram_cfg = CFG_DDR_CONTROL;
244 asm("sync; isync; msync");
247 return (CFG_SDRAM_SIZE * 1024 * 1024);
249 #endif /* !defined(CONFIG_SPD_EEPROM) */