2 * (C) Copyright 2002,2003, Motorola Inc.
3 * Xianghua Xiao, (X.Xiao@motorola.com)
5 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 #include <asm/processor.h>
28 #include <asm/immap_85xx.h>
29 #include <spd_sdram.h>
31 long int fixed_sdram (void);
33 int board_pre_init (void)
35 #if defined(CONFIG_PCI)
36 volatile ccsr_pcix_t *pci = (void *)(CFG_MPC85xx_PCIX_ADDR);
38 pci->peer &= 0xffffffdf; /* disable master abort */
47 get_sys_info (&sysinfo);
49 printf ("Board: Freescale MPC8540EVAL Board\n");
50 printf ("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000);
51 printf ("\tCCB: %lu MHz\n", sysinfo.freqSystemBus / 1000000);
52 printf ("\tDDR: %lu MHz\n", sysinfo.freqSystemBus / 2000000);
53 if((CFG_LBC_LCRR & 0x0f) == 2 || (CFG_LBC_LCRR & 0x0f) == 4 \
54 || (CFG_LBC_LCRR & 0x0f) == 8) {
55 printf ("\tLBC: %lu MHz\n",
56 sysinfo.freqSystemBus / 1000000/(CFG_LBC_LCRR & 0x0f));
58 printf("\tLBC: unknown\n");
60 printf("L1 D-cache 32KB, L1 I-cache 32KB enabled.\n");
64 phys_size_t initdram (int board_type)
68 #if !defined(CONFIG_RAM_AS_FLASH)
69 volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
73 #if !defined(CONFIG_RAM_AS_FLASH) || defined(CONFIG_DDR_DLL)
74 volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
77 #if defined(CONFIG_DDR_DLL)
80 /* Work around to stabilize DDR DLL */
81 temp_ddrdll = gur->ddrdllcr;
82 gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000;
83 asm("sync;isync;msync");
86 #if defined(CONFIG_SPD_EEPROM)
87 dram_size = spd_sdram ();
89 dram_size = fixed_sdram ();
92 #if defined(CFG_RAMBOOT)
96 #if !defined(CONFIG_RAM_AS_FLASH) /* LocalBus is not emulating flash */
97 get_sys_info(&sysinfo);
98 /* if localbus freq is less than 66Mhz,we use bypass mode,otherwise use DLL */
99 if(sysinfo.freqSystemBus/(CFG_LBC_LCRR & 0x0f) < 66000000) {
100 lbc->lcrr = (CFG_LBC_LCRR & 0x0fffffff)| 0x80000000;
102 lbc->lcrr = CFG_LBC_LCRR & 0x7fffffff;
104 temp_lbcdll = gur->lbcdllcr;
105 gur->lbcdllcr = ((temp_lbcdll & 0xff) << 16 ) | 0x80000000;
106 asm("sync;isync;msync");
108 lbc->or2 = CFG_OR2_PRELIM; /* 64MB SDRAM */
109 lbc->br2 = CFG_BR2_PRELIM;
110 lbc->lbcr = CFG_LBC_LBCR;
111 lbc->lsdmr = CFG_LBC_LSDMR_1;
113 * (ulong *)0 = 0x000000ff;
114 lbc->lsdmr = CFG_LBC_LSDMR_2;
116 * (ulong *)0 = 0x000000ff;
117 lbc->lsdmr = CFG_LBC_LSDMR_3;
119 * (ulong *)0 = 0x000000ff;
120 lbc->lsdmr = CFG_LBC_LSDMR_4;
122 * (ulong *)0 = 0x000000ff;
123 lbc->lsdmr = CFG_LBC_LSDMR_5;
125 lbc->lsrt = CFG_LBC_LSRT;
127 lbc->mrtpr = CFG_LBC_MRTPR;
131 #if defined(CONFIG_DDR_ECC)
133 /* Initialize all of memory for ECC, then
137 volatile ccsr_ddr_t *ddr= (void *)(CFG_MPC85xx_DDR_ADDR);
139 for (*p = 0; p < (uint *)(8 * 1024); p++) {
140 if (((unsigned int)p & 0x1f) == 0) { dcbz(p); }
141 *p = (unsigned int)0xdeadbeef;
142 if (((unsigned int)p & 0x1c) == 0x1c) { dcbf(p); }
146 dma_xfer((uint *)0x2000,0x2000,(uint *)0);
148 dma_xfer((uint *)0x4000,0x4000,(uint *)0);
150 dma_xfer((uint *)0x8000,0x8000,(uint *)0);
152 dma_xfer((uint *)0x10000,0x10000,(uint *)0);
154 dma_xfer((uint *)0x20000,0x20000,(uint *)0);
156 dma_xfer((uint *)0x40000,0x40000,(uint *)0);
158 dma_xfer((uint *)0x80000,0x80000,(uint *)0);
160 dma_xfer((uint *)0x100000,0x100000,(uint *)0);
162 dma_xfer((uint *)0x200000,0x200000,(uint *)0);
164 dma_xfer((uint *)0x400000,0x400000,(uint *)0);
166 for (i = 1; i < dram_size / 0x800000; i++) {
167 dma_xfer((uint *)(0x800000*i),0x800000,(uint *)0);
170 /* Enable errors for ECC */
171 ddr->err_disable = 0x00000000;
172 asm("sync;isync;msync");
179 #if defined(CFG_DRAM_TEST)
182 uint *pstart = (uint *) CFG_MEMTEST_START;
183 uint *pend = (uint *) CFG_MEMTEST_END;
186 printf("SDRAM test phase 1:\n");
187 for (p = pstart; p < pend; p++)
190 for (p = pstart; p < pend; p++) {
191 if (*p != 0xaaaaaaaa) {
192 printf ("SDRAM test fails at: %08x\n", (uint) p);
197 printf("SDRAM test phase 2:\n");
198 for (p = pstart; p < pend; p++)
201 for (p = pstart; p < pend; p++) {
202 if (*p != 0x55555555) {
203 printf ("SDRAM test fails at: %08x\n", (uint) p);
208 printf("SDRAM test passed.\n");
213 #if !defined(CONFIG_SPD_EEPROM)
214 /*************************************************************************
215 * fixed sdram init -- doesn't use serial presence detect.
216 ************************************************************************/
217 long int fixed_sdram (void)
220 volatile ccsr_ddr_t *ddr= (void *)(CFG_MPC85xx_DDR_ADDR);
222 ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
223 ddr->cs0_config = CFG_DDR_CS0_CONFIG;
224 ddr->timing_cfg_1 = CFG_DDR_TIMING_1;
225 ddr->timing_cfg_2 = CFG_DDR_TIMING_2;
226 ddr->sdram_mode = CFG_DDR_MODE;
227 ddr->sdram_interval = CFG_DDR_INTERVAL;
228 #if defined (CONFIG_DDR_ECC)
229 ddr->err_disable = 0x0000000D;
230 ddr->err_sbe = 0x00ff0000;
232 asm("sync;isync;msync");
234 #if defined (CONFIG_DDR_ECC)
235 /* Enable ECC checking */
236 ddr->sdram_cfg = (CFG_DDR_CONTROL | 0x20000000);
238 ddr->sdram_cfg = CFG_DDR_CONTROL;
240 asm("sync; isync; msync");
243 return (CFG_SDRAM_SIZE * 1024 * 1024);
245 #endif /* !defined(CONFIG_SPD_EEPROM) */