2 * Copyright (C) 2002,2003, Motorola Inc.
3 * Xianghua Xiao <X.Xiao@motorola.com>
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 #include <ppc_asm.tmpl>
26 #include <asm/cache.h>
40 /* TLB1 entries configuration: */
42 .section .bootpg, "ax"
47 .long 0x0a /* the following data table uses a few of 16 TLB entries */
49 .long FSL_BOOKE_MAS0(1,1,0)
50 .long FSL_BOOKE_MAS1(1,1,0,0,BOOKE_PAGESZ_1M)
51 .long FSL_BOOKE_MAS2(CFG_CCSRBAR,(MAS2_I|MAS2_G))
52 .long FSL_BOOKE_MAS3(CFG_CCSRBAR,0,(MAS3_SX|MAS3_SW|MAS3_SR))
54 #if defined(CFG_FLASH_PORT_WIDTH_16)
55 .long FSL_BOOKE_MAS0(1,2,0)
56 .long FSL_BOOKE_MAS1(1,1,0,0,BOOKE_PAGESZ_4M)
57 .long FSL_BOOKE_MAS2(CFG_FLASH_BASE,(MAS2_I|MAS2_G))
58 .long FSL_BOOKE_MAS3(CFG_FLASH_BASE,0,(MAS3_SX|MAS3_SW|MAS3_SR))
60 .long FSL_BOOKE_MAS0(1,3,0)
61 .long FSL_BOOKE_MAS1(1,1,0,0,BOOKE_PAGESZ_4M)
62 .long FSL_BOOKE_MAS2(CFG_FLASH_BASE+0x400000,(MAS2_I|MAS2_G))
63 .long FSL_BOOKE_MAS3(CFG_FLASH_BASE+0x400000,0,(MAS3_SX|MAS3_SW|MAS3_SR))
65 .long FSL_BOOKE_MAS0(1,2,0)
66 .long FSL_BOOKE_MAS1(1,1,0,0,BOOKE_PAGESZ_16M)
67 .long FSL_BOOKE_MAS2(CFG_FLASH_BASE,(MAS2_I|MAS2_G))
68 .long FSL_BOOKE_MAS3(CFG_FLASH_BASE,0,(MAS3_SX|MAS3_SW|MAS3_SR))
70 .long FSL_BOOKE_MAS0(1,3,0)
71 .long FSL_BOOKE_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
72 .long FSL_BOOKE_MAS2(0,0)
73 .long FSL_BOOKE_MAS3(0,0,(MAS3_SX|MAS3_SW|MAS3_SR))
76 #if !defined(CONFIG_SPD_EEPROM)
77 .long FSL_BOOKE_MAS0(1,4,0)
78 .long FSL_BOOKE_MAS1(1,1,0,0,BOOKE_PAGESZ_64M)
79 .long FSL_BOOKE_MAS2(CFG_DDR_SDRAM_BASE,0)
80 .long FSL_BOOKE_MAS3(CFG_DDR_SDRAM_BASE,0,(MAS3_SX|MAS3_SW|MAS3_SR))
82 .long FSL_BOOKE_MAS0(1,5,0)
83 .long FSL_BOOKE_MAS1(1,1,0,0,BOOKE_PAGESZ_64M)
84 .long FSL_BOOKE_MAS2(CFG_DDR_SDRAM_BASE+0x4000000,0)
85 .long FSL_BOOKE_MAS3(CFG_DDR_SDRAM_BASE+0x4000000,0,(MAS3_SX|MAS3_SW|MAS3_SR))
87 .long FSL_BOOKE_MAS0(1,4,0)
88 .long FSL_BOOKE_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
89 .long FSL_BOOKE_MAS2(0,0)
90 .long FSL_BOOKE_MAS3(0,0,(MAS3_SX|MAS3_SW|MAS3_SR))
92 .long FSL_BOOKE_MAS0(1,5,0)
93 .long FSL_BOOKE_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
94 .long FSL_BOOKE_MAS2(0,0)
95 .long FSL_BOOKE_MAS3(0,0,(MAS3_SX|MAS3_SW|MAS3_SR))
98 .long FSL_BOOKE_MAS0(1,6,0)
99 .long FSL_BOOKE_MAS1(1,1,0,0,BOOKE_PAGESZ_64M)
100 #if defined(CONFIG_RAM_AS_FLASH)
101 .long FSL_BOOKE_MAS2(CFG_LBC_SDRAM_BASE,(MAS2_I|MAS2_G))
103 .long FSL_BOOKE_MAS2(CFG_LBC_SDRAM_BASE,0)
105 .long FSL_BOOKE_MAS3(CFG_LBC_SDRAM_BASE,0,(MAS3_SX|MAS3_SW|MAS3_SR))
107 .long FSL_BOOKE_MAS0(1,7,0)
108 .long FSL_BOOKE_MAS1(1,1,0,0,BOOKE_PAGESZ_16K)
109 #ifdef CONFIG_L2_INIT_RAM
110 .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR,0,0,0,1,0,0,0,0)
112 .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR,0)
114 .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR,0,(MAS3_SX|MAS3_SW|MAS3_SR))
116 .long FSL_BOOKE_MAS0(1,8,0)
117 .long FSL_BOOKE_MAS1(1,1,0,0,BOOKE_PAGESZ_256M)
118 .long FSL_BOOKE_MAS2(CFG_PCI_MEM_BASE,(MAS2_I|MAS2_G))
119 .long FSL_BOOKE_MAS3(CFG_PCI_MEM_BASE,0,(MAS3_SX|MAS3_SW|MAS3_SR))
121 .long FSL_BOOKE_MAS0(1,9,0)
122 .long FSL_BOOKE_MAS1(1,1,0,0,BOOKE_PAGESZ_16K)
123 .long FSL_BOOKE_MAS2(CFG_BCSR,(MAS2_I|MAS2_G))
124 .long FSL_BOOKE_MAS3(CFG_BCSR,0,(MAS3_SX|MAS3_SW|MAS3_SR))
126 #if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
127 .long FSL_BOOKE_MAS0(1,15,0)
128 .long FSL_BOOKE_MAS1(1,1,0,0,BOOKE_PAGESZ_1M)
129 .long FSL_BOOKE_MAS2(CFG_CCSRBAR_DEFAULT,(MAS2_I|MAS2_G))
130 .long FSL_BOOKE_MAS3(CFG_CCSRBAR_DEFAULT,0,(MAS3_SX|MAS3_SW|MAS3_SR))
132 .long FSL_BOOKE_MAS0(1,15,0)
133 .long FSL_BOOKE_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
134 .long FSL_BOOKE_MAS2(0,0)
135 .long FSL_BOOKE_MAS3(0,0,(MAS3_SX|MAS3_SW|MAS3_SR))
139 /* LAW(Local Access Window) configuration:
140 * 0000_0000-0800_0000: DDR(128M) -or- larger
141 * f000_0000-f3ff_ffff: PCI(256M)
142 * f400_0000-f7ff_ffff: RapidIO(128M)
143 * f800_0000-ffff_ffff: localbus(128M)
144 * f800_0000-fbff_ffff: LBC SDRAM(64M)
145 * fc00_0000-fdef_ffff: LBC BCSR,RTC,etc(31M)
146 * fdf0_0000-fdff_ffff: CCSRBAR(1M)
147 * fe00_0000-ffff_ffff: Flash(32M)
148 * Note: CCSRBAR and L2-as-SRAM don't need configure Local Access
150 * Note: If flash is 8M at default position(last 8M),no LAW needed.
153 #if !defined(CONFIG_SPD_EEPROM)
154 #define LAWBAR0 ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff)
155 #define LAWAR0 (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M))
158 #define LAWAR0 ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN)
161 #define LAWBAR1 ((CFG_PCI_MEM_BASE>>12) & 0xfffff)
162 #define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_256M))
164 #if !defined(CONFIG_RAM_AS_FLASH)
165 #define LAWBAR2 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff)
166 #define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_128M))
169 #define LAWAR2 ((LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN)
172 .section .bootpg, "ax"
177 .long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2