2 * Copyright 2004 Freescale Semiconductor.
3 * (C) Copyright 2002,2003, Motorola Inc.
4 * Xianghua Xiao, (X.Xiao@motorola.com)
6 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 #include <asm/processor.h>
31 #include <asm/immap_85xx.h>
34 #if defined(CONFIG_OF_FLAT_TREE)
36 extern void ft_cpu_setup(void *blob, bd_t *bd);
40 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
41 extern void ddr_enable_ecc(unsigned int dram_size);
44 extern long int spd_sdram(void);
46 void local_bus_init(void);
47 void sdram_init(void);
48 long int fixed_sdram(void);
51 int board_early_init_f (void)
61 printf(" PCI1: 32 bit, %d MHz (compiled)\n",
62 CONFIG_SYS_CLK_FREQ / 1000000);
64 printf(" PCI1: disabled\n");
68 * Initialize local bus.
77 initdram(int board_type)
80 extern long spd_sdram (void);
81 volatile immap_t *immap = (immap_t *)CFG_IMMR;
83 puts("Initializing\n");
85 #if defined(CONFIG_DDR_DLL)
87 volatile ccsr_gur_t *gur= &immap->im_gur;
91 * Work around to stabilize DDR DLL
93 temp_ddrdll = gur->ddrdllcr;
94 gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000;
95 asm("sync;isync;msync");
99 #if defined(CONFIG_SPD_EEPROM)
100 dram_size = spd_sdram ();
102 dram_size = fixed_sdram ();
105 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
107 * Initialize and enable DDR ECC.
109 ddr_enable_ecc(dram_size);
123 * Initialize Local Bus
129 volatile immap_t *immap = (immap_t *)CFG_IMMR;
130 volatile ccsr_gur_t *gur = &immap->im_gur;
131 volatile ccsr_lbc_t *lbc = &immap->im_lbc;
139 * Fix Local Bus clock glitch when DLL is enabled.
141 * If localbus freq is < 66Mhz, DLL bypass mode must be used.
142 * If localbus freq is > 133Mhz, DLL can be safely enabled.
143 * Between 66 and 133, the DLL is enabled with an override workaround.
146 get_sys_info(&sysinfo);
147 clkdiv = lbc->lcrr & 0x0f;
148 lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
151 lbc->lcrr = CFG_LBC_LCRR | 0x80000000; /* DLL Bypass */
153 } else if (lbc_hz >= 133) {
154 lbc->lcrr = CFG_LBC_LCRR & (~0x80000000); /* DLL Enabled */
158 * On REV1 boards, need to change CLKDIV before enable DLL.
159 * Default CLKDIV is 8, change it to 4 temporarily.
161 uint pvr = get_pvr();
162 uint temp_lbcdll = 0;
164 if (pvr == PVR_85xx_REV1) {
165 /* FIXME: Justify the high bit here. */
166 lbc->lcrr = 0x10000004;
169 lbc->lcrr = CFG_LBC_LCRR & (~0x80000000); /* DLL Enabled */
173 * Sample LBC DLL ctrl reg, upshift it to set the
176 temp_lbcdll = gur->lbcdllcr;
177 gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000);
178 asm("sync;isync;msync");
184 * Initialize SDRAM memory on the Local Bus.
190 volatile immap_t *immap = (immap_t *)CFG_IMMR;
191 volatile ccsr_lbc_t *lbc= &immap->im_lbc;
192 uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
195 print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
198 * Setup SDRAM Base and Option Registers
200 lbc->or2 = CFG_OR2_PRELIM;
201 lbc->br2 = CFG_BR2_PRELIM;
202 lbc->lbcr = CFG_LBC_LBCR;
205 lbc->lsrt = CFG_LBC_LSRT;
206 lbc->mrtpr = CFG_LBC_MRTPR;
210 * Configure the SDRAM controller.
212 lbc->lsdmr = CFG_LBC_LSDMR_1;
215 ppcDcbf((unsigned long) sdram_addr);
218 lbc->lsdmr = CFG_LBC_LSDMR_2;
221 ppcDcbf((unsigned long) sdram_addr);
224 lbc->lsdmr = CFG_LBC_LSDMR_3;
227 ppcDcbf((unsigned long) sdram_addr);
230 lbc->lsdmr = CFG_LBC_LSDMR_4;
233 ppcDcbf((unsigned long) sdram_addr);
236 lbc->lsdmr = CFG_LBC_LSDMR_5;
239 ppcDcbf((unsigned long) sdram_addr);
244 #if defined(CFG_DRAM_TEST)
247 uint *pstart = (uint *) CFG_MEMTEST_START;
248 uint *pend = (uint *) CFG_MEMTEST_END;
251 printf("SDRAM test phase 1:\n");
252 for (p = pstart; p < pend; p++)
255 for (p = pstart; p < pend; p++) {
256 if (*p != 0xaaaaaaaa) {
257 printf ("SDRAM test fails at: %08x\n", (uint) p);
262 printf("SDRAM test phase 2:\n");
263 for (p = pstart; p < pend; p++)
266 for (p = pstart; p < pend; p++) {
267 if (*p != 0x55555555) {
268 printf ("SDRAM test fails at: %08x\n", (uint) p);
273 printf("SDRAM test passed.\n");
279 #if !defined(CONFIG_SPD_EEPROM)
280 /*************************************************************************
281 * fixed sdram init -- doesn't use serial presence detect.
282 ************************************************************************/
283 long int fixed_sdram (void)
286 volatile immap_t *immap = (immap_t *)CFG_IMMR;
287 volatile ccsr_ddr_t *ddr= &immap->im_ddr;
289 ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
290 ddr->cs0_config = CFG_DDR_CS0_CONFIG;
291 ddr->timing_cfg_1 = CFG_DDR_TIMING_1;
292 ddr->timing_cfg_2 = CFG_DDR_TIMING_2;
293 ddr->sdram_mode = CFG_DDR_MODE;
294 ddr->sdram_interval = CFG_DDR_INTERVAL;
295 #if defined (CONFIG_DDR_ECC)
296 ddr->err_disable = 0x0000000D;
297 ddr->err_sbe = 0x00ff0000;
299 asm("sync;isync;msync");
301 #if defined (CONFIG_DDR_ECC)
302 /* Enable ECC checking */
303 ddr->sdram_cfg = (CFG_DDR_CONTROL | 0x20000000);
305 ddr->sdram_cfg = CFG_DDR_CONTROL;
307 asm("sync; isync; msync");
310 return CFG_SDRAM_SIZE * 1024 * 1024;
312 #endif /* !defined(CONFIG_SPD_EEPROM) */
315 #if defined(CONFIG_PCI)
317 * Initialize PCI Devices, report devices found.
321 static struct pci_controller hose;
323 #endif /* CONFIG_PCI */
330 extern void pci_mpc85xx_init(struct pci_controller *hose);
332 pci_mpc85xx_init(&hose);
333 #endif /* CONFIG_PCI */
337 #if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
339 ft_board_setup(void *blob, bd_t *bd)
345 ft_pci_setup(blob, bd);
347 ft_cpu_setup(blob, bd);
349 p = ft_get_prop(blob, "/memory/reg", &len);
351 *p++ = cpu_to_be32(bd->bi_memstart);
352 *p = cpu_to_be32(bd->bi_memsize);